Homework

    Homework 3 - due Monday, May 3, 11:59pm (submission using Blackboard, section ECE-448-001).

    Homework 3 solutions (except Task 4; mm=4)

    Homework 2 - due Monday, April 26, 11:59pm (submission using Blackboard, section ECE-448-001).

    Homework 2 solutions (by Robert Wallace)

    Homework 1 - due Saturday, April 10, 11:59pm (submission using Blackboard, section ECE-448-001).

    Homework 1 solutions (mm=10, dd=6; by Ethan Li)

General Laboratory Rules

• Each lab assignment will be preceded by an introduction and a hands-on session taught by a TA.
   
• Selected lab sessions will include lab exercises, aimed at helping you to prepare for the actual lab assignments. Solutions to lab exercises submitted using Blackboard and demonstrated before the end of the lab session will be rewarded with 25% bonus points. The remaining students can submit lab exercise deliverables within 24 hours from the end of their respective lab session. In this case, only a video demonstration is required.
   
• The deadlines for submitting all lab assignment deliverables (including source code, diagrams, waveforms, configuration files, lab reports, video demonstrations, etc.) are being set as follows:
  
  • Tuesday section - Tuesday, 8:30 AM
  • Wednesday section - Wednesday, 6:50 PM
  • Friday section - Friday, 8:10 AM.
   
• Each lab assignment that is one week late will be penalized by deducting 1/3 of its allocated points. No credit will be received for a lab experiment that is more than one week late. Opportunities will be provided to earn bonus points by completing additional tasks for each assignment. Both penalty and bonus points will apply independently to the demonstrations and to the electronic deliverables.
   
• During the second part of the semester, the students can follow two schedules:
• Schedule A:  Lab 4 - 2 weeks, Lab 5 - 2 weeks, Lab 6 - 2 weeks.
• Schedule B:   Lab 4 - 3 weeks, Lab 5 or Lab 6 - 3 weeks. One lab is not attempted, and as a result its grade is set to 0.
  Schedule B is intended for students who feel that they fall behind, and need more time for Labs 4-6. These students can avoid late submission penalties, but at the same time, they have to give up their chance of earning points for one of the two last labs, Lab 5 or Lab 6 (8 points). A decision about switching to Schedule B, should be communicated to the respective lab instructor no later than by the regular deadline for Lab 4 according to Schedule A.
   
• Students who do well in Labs 1-3 can sign up for Schedule A+.
  This schedule will involve working on an open-ended project proposed by the students, the TA, or the instructor.
  The project can be done individually or in groups of two students. The schedule of the project must include the following steps:

• draft specification  - 1 week
• revised specification approved by the instructor and the TA - 1 week
• milestone 1 - 2 weeks
• milestone 2 - 2 weeks
• final report & deliverables - 1 week.

• Office hours will be devoted to helping students with their designs and answering any questions related to the subject of the course.
   
• Students are required to work individually on most assignments, unless group work is clearly stated in the text of the assignment. In case of group work, all members of the team are expected to be intimately familiar with the entire solution to the given lab assignment and the entire lab report. This knowledge will be verified during the experiment demonstration and the same grade will be applied to the entire team.
   
• Every completed experiment must be documented using a video demonstration. It is the student's responsibility to convince the TA that their designs work as required. Therefore, students have to simulate and test their designs thoroughly and well document their work. The TA is not required to test anything by himself nor to investigate if the designs are correct in case of insufficient documentation.
   
• In order to prevent cheating and plagiarism, the students will be required to
  • submit all electronic deliverables using Blackboard at the designated time
  • answer correctly several detailed questions regarding their solutions during a Q&A session with the TA.
  Not complying with either of these requirements may lead to either a total rejection of the demonstration by the TA, or to a substantial reduction of the number of points awarded to the student.
   
• In case of any evident attempt to submit somebody's else work as your own, both students involved in the incident may be penalized by taking away all points for the given lab assignment. The two repeated attempts to present somebody's else work as your own may lead to the F grade for the entire course, independently of the total amount of points earned by the student before the second incident.
   
• The students are encouraged to help and support each other in all problems related to the
  - operation of the CAD tools,
  - operation of the FPGA boards,
  - operation of the measurement equipment available in the lab,
  - understanding of the problem to be solved during each experiment.
   

Lab Assignments

Please submit all solutions using Blackboard.

Lab Assignment 6: The LightsOut Puzzle with the Display on a Monitor Screen

Lab Assignment 5: Using an FPro SoC with Custom Hardware Accelerators: Fast Sorting.

Lab Assignment 4: The LightsOut Puzzle Implemented Using the FPro System.

Lab Assignment 3: Finite State Machines. Bus Ticket Dispensing Machine.

Lab Assignment 2: Implementing Combinational and Sequential Logic in VHDL.

Lab Assignment 1: Developing and Using Effective Testbenches.

The specifications of lab assignments will be posted gradually here on the days when each lab assignment is introduced for the first time (typically Tuesdays).

Lab Slides & Examples

Lab Lecture 6: Implementing the LightsOut Puzzle with the display on a monitor screen.

Lab Lecture 5: Software/Hardware Co-design Using the FPro System.

Lab Lecture 4: Developing an FPro SoC with standard & custom hardware IP cores.

Lab Lecture 3: FPGA Design Flow. Using Seven-Segment Displays, Buttons, and Switches. Design of Controllers Using ASM Charts.

Lab Lecture 2: Implementing Combinational and Sequential Logic in VHDL. Simulation using ModelSim Intel FPGA.

Lab Lecture 1: Developing Effective Testbenches. Simulation using Xilinx Vivado Simulator.

Lab slides and examples will be posted gradually here on the days when each lab assignment is introduced for the first time (typically Tuesdays).

Software

• Xilinx Vivado Design Suite
• ModelSim Intel FPGA

• Xilinx Vivado Installation Instructions
• Resources on Simulators
• Using Vivado for Synthesis, Implementation, and Timing Analysis

FREE versions can be installed on your laptops and home workstations.

Hardware

• Digilent Basys 3 Artix-7 FPGA Trainer Board
  
• Digilent Basys 3 FPGA Board Reference Manual
  
• Digilent Adept 2
• Artix-7 FPGA Family
  
• Artix-7 FPGA Family User Guides
  

Useful References

VHDL

VHDL Instructions: Templates & Examples

VHDL-2008: Why It Matters

Vivado Design Suite User Guide: Synthesis

OpenCores Coding Guidelines

The Low Carb VHDL Tutorial - by Bryan Mealy

Frequently Asked Questions And Answers about VHDL (Part 1): General from comp.lang.vhdl

Frequently Asked Questions And Answers about VHDL (Part 4): VHDL Glossary from comp.lang.vhdl

C

Top 10 C Language resources that will turn you into a better programmer

C Tutorial

 

Past Exams

Past Lab Exams

Lab Midterm Exam from Spring 2021 - Tuesday Section

Solutions by Javad Bahrami: Deliverables

Lab Midterm Exam from Spring 2021 - Wednesday Section

Solutions by Robert DeCoito: Deliverables

Lab Midterm Exam from Spring 2021 - Friday Section

Solutions by Javad Bahrami: Deliverables

Lab Midterm Exam from Spring 2020 - Tuesday Section

Solutions by Javad Bahrami: Source_files  Timing Waveform 1  Timing Waveform 2  Timing Waveform 3  Resource Utilization

Lab Midterm Exam from Spring 2020 - Wednesday Section

Solutions by Jamil Al Kallas (with corrections and extensions by the instructors): Source_files  Timing Waveforms  Resource Utilization

Lab Midterm Exam from Spring 2020 - Friday Section

Solutions by Timothy Bullock (with corrections and extensions by the instructors): Source_files  Timing Waveforms  Resource Utilization

Lab Midterm Exam from Spring 2019 - Tuesday Section

Solutions by Kevin Riley: toplevel.vhd  testbench.vhd  Basys-3-Master.xdc  Functional Waveform  Timing Waveform  Midterm Report

Lab Midterm Exam from Spring 2019 - Wednesday Section

Solutions by Spencer Lombardo: toplevel.vhd  datapath.vhd  asm.vhd  toplevel_tb.vhd  Functional Waveform  Timing Waveform  Timing Report

Lab Midterm Exam from Spring 2016 - Monday Section

Solutions: Datapath.vhd  Controller.vhd  Statistics.vhd  testbench.vhd

Lab Midterm Exam from Spring 2016 - Tuesday Section

Solutions: Reg.vhd  Counter.vhd  ram.vhd  Datapath.vhd  Controller.vhd  Sort.vhd  Sort_tb.vhd

Lab Midterm Exam from Spring 2016 - Wednesday Section

Solutions: vrot.vhd  vrot_tb.vhd  sqrt_CORDIC.vhd  sqrt_CORDIC_tb.vhd

Lab Midterm Exam from Spring 2014 - Monday Section

Solutions: up_counter.vhd  shiftn.vhd  datapath.vhd  controller.vhd  top.vhd  top_tb.vhd  func_sim_waveform.pdf

Lab Midterm Exam from Spring 2014 - Thursday Section

Solutions: regn.vhd  lfsr.vhd  counter.vhd  datapath.vhd  controller.vhd  midterm_thursday.vhd  midterm_thursday_tb.vhd  func_sim_waveform.pdf  solutions_to_tasks_4-6.pdf

Lab Midterm Exam from Spring 2013 - Wednesday Section

Solutions: regn.vhd  counter.vhd  lfsr.vhd  PISO.vhd  SIPO.vhd  midterm_wednesday.vhd  midterm_wednesday_TB.vhd  Functional_simulation_waveforms.pdf  Timing_simulations_waveforms_ISim.pdf  Timing_simulations_waveforms_Aldec.pdf  Tasks_4-6.pdf

Lab Midterm Exam from Spring 2013 - Thursday Section

Solutions: regn.vhd  counter.vhd  midterm_thursday.vhd  midterm_Thursday_TB.vhd  Functional_simulation_waveforms.pdf  Tasks_4-6.pdf

Lab Midterm Exam from Spring 2012 - Tuesday Section

Solutions: reg.vhd  shiftn.vhd  MidTerm_201.vhd  MidTerm_201_TB.vhd  Waveform.pdf  Report.pdf

Lab Midterm Exam from Spring 2012 - Thursday Section

Solutions: reg.vhd  shift1.vhd  shiftn.vhd  counter.vhd  datapath.vhd  controller.vhd  MidTerm_203.vhd  MidTerm_203_TB.vhd  Waveform.pdf  Report.pdf

Lab Midterm Exam from Spring 2011 - Monday Section

Solutions:  ma_ppd_pkg.vhd   ma_ppd.vhd   ma_ppd_tb.vhd

Lab Midterm Exam from Spring 2011 - Tuesday Section

Lab Midterm Exam from Spring 2011 - Wednesday Section

Solutions:   regn.vhd   AV4.vhd   AV4_test.vhd

Lab Midterm Exam from Spring 2011 - Thursday Section

Solutions:  regn.vhd  full_adder.vhd  half_adder.vhd  madd.vhd  avg.vhd  avg_tb.vhd

Lab Midterm Exam from Spring 2010 - Monday Section

Solutions:   dgs.vhd   dgs_tb.vhd

Lab Midterm Exam from Spring 2010 - Tuesday Section

Solutions:   int-comb.vhd   cic.vhd   cic_tb.vhd

Lab Midterm Exam from Spring 2010 - Wednesday Section

Solutions:   grain128_pkg.vhd   grain128.vhd   grain128_tb.vhd

Lab Midterm Exam from Spring 2010 - Thursday Section

Solutions:   systolic_block.vhd   systolic_mult.vhd   systolic_mult_tb.vhd

Lab Midterm Exam from Spring 2008 - Tuesday Section

Lab Midterm Exam from Spring 2008 - Wednesday Section

Lab Midterm Exam from Spring 2008 - Thursday Section

Lab Midterm Exam from Spring 2007 - Tuesday Section

Lab Midterm Exam from Spring 2007 - Wednesday Section

Past Quizzes

Quizzes from Spring 2006

Quiz 1

Quiz 2 with solutions

Quiz 3

Quiz 4 with solutions

Quiz 5 with solutions

Quizzes from Spring 2013

Quiz 1

Quiz 2, Quiz 2 solutions

Quiz 3 Quiz 3 solutions

Past Midterm Exams for the Lecture

Midterm Exam from Spring 2021:

Text of the exam  Grading scheme    Solutions

Midterm Exam from Spring 2020:

Text of the exam for Group 1  Solutions for Group 1

Text of the exam for Group 2  Solutions for Group 2

Midterm Exam from Spring 2019:

Text of the exam for Group 1  Solutions for Group 1

Text of the exam for Group 2  Solutions for Group 2

Midterm Exam from Spring 2016:

Text of the exam  Answer sheet   Solutions

Midterm Exam from Spring 2015:

Text of the exam  Answer sheet   Solutions

Source Codes:   Controller (Problems 1 & 4):   controller.vhd   controller_tb.vhd   Variable Arithmetic Shifter Right (Problem 3): fixed_shifter_right.vhd   variable_shifter_right.vhd   variable_shifter_right_tb.vhd

Midterm Exam from Spring 2014:

Text of the exam

Midterm Exam from Spring 2013:

Text of the exam  Answer sheet   Solutions

Midterm Exam from Spring 2012

Solutions: Problem 1, Problem 2, Problem 3, Problem 4: piso.vhd, piso_inst.vhd

Midterm Exam from Spring 2011:    Group 1    Group 2    distribution of grades

Solutions for Group 1:  Problem 1, Problem 2: NFSR_1.vhd, F.vhd, NFSR_1_tb.vhd   Resource Utilization

Solutions for Group 2:  Problem 1, Problem 2: NFSR_2.vhd, F.vhd, NFSR_2_tb.vhd   Resource Utilization

Midterm Exam from Spring 2010

Solutions: Task 1: bsm.vhd   Task 2: bsm_tb.vhd  Task 3: solution

Past Final Exams

Final Exam from Spring 2020

Exam

Final Exam from Spring 2019

Group 1

Group 2

Final Exam from Spring 2015: Part 1, Part 2

Final Exam from Spring 2014: Part 1, Part 2

Final Exam from Spring 2013: Part 1, Part 2

Solutions: Part 1, Part 2

Final Exam from Spring 2012

Final Exam Part I - Group 1

Final Exam Part I - Group 2

Final Exam Part II

Solutions: P1_1.jpg, P1_2.jpg, P2.jpg, P3_Task1_1.jpg, P3_Task1_2.jpg, P3_Task2.pdf

Final Exam from Spring 2011

Final Exam Part I - Group 1

Final Exam Part I - Group 2

Final Exam Part II

Solutions: P1_Block_diagram.jpg, P2_ASM_chart.jpg, P3_PicoBlaze_program.jpg