Kris Gaj
The Nguyen Engineering Building, room 3225
e-mail: kgaj (at) gmu.edu
Please start a subject of your e-mail from "ECE 448:"
Dilip Epparapalli
e-mail: depparap (at) gmu.edu
Please start a subject of your e-mail from "ECE 448:"
Dilip Epparapalli:
- In person: Wednesday, Thursday, 4:00-6:00 PM, ENGR 3208
Kris Gaj:
Please send an e-mail request or private Piazza request, including the day and time slot suitable for you.
- In person: Tuesday, Thursday, 1:00-2:00 PM, ENGR 3225
- Zoom: by appointment
Lab assignments: 40% Lab exercises: 4% Midterm exam for the lab: 15% Quizzes and homework: 6% Midterm exam for the lecture: 10% Final exam: 25% Class & Piazza activity: 5% bonus
Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC , Wiley, 2017, 2nd edition, ISBN-13: 978-1119282747.
- Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 2008 © 3rd edition.
- Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006.
- Ricardo Jasinski, Effective Coding with VHDL: Principles and Best Practice, The MIT Press, 2016 © 1st edition.
Lecture 25 - RTL Design Methodology. [pptx, pdf]
Lecture 24 - Lab 6 Hints. Timing Analysis. [pptx, pdf]
- Timing Analysis – Class Exercise 1 (including solutions)
- Timing Analysis – Class Exercise 2 (including solutions)
Lecture 23 - The FPro Video Subsystem: On-Screen-Display (OSD) Core and Its Driver. [pptx, pdf]
Lecture 22 - Video Cores. [pptx, pdf]
Lecture 21 - The FPro Video Subsystem: VGA Display & Frame Buffer Core. [pptx, pdf]
Lecture 20 - Software/Hardware Co-design Using the FPro System. Part 3: I/O Register Map and a Wrapper of the Sorting Core. [pptx, pdf]
Lecture 19b - I/O Register Map of an MMIO Core. Part 2: Simplified Address Decoding. [pptx, pdf]
Lecture 19a - I/O Register Map of an MMIO Core. Part 1: Exact Address Decoding. [pptx, pdf]
Lecture 18 - Software/Hardware Co-design Using the FPro System. Part 2: Sorting Core. [pptx, pdf]
Lecture 17 - Software/Hardware Co-design Using the FPro System. Part 1: Sorting Core. [pptx, pdf]
Lecture 16 - Drivers of the LED-MUX Core & Debouncing Core. [pptx, pdf]
Lecture 15 - Bare Metal System Software Development. [pptx, pdf]
- C++ What is Object-Oriented Programming? What are Classes and Objects?
- C++ Classes and Objects
- C++ Class Methods
- C++ Constructors
- C++ Access Specifiers
- C++ Encapsulation
- C++ Enumeration
Lecture 14 - Introduction to the FPro System. [pptx, pdf]
Midterm Exam for the Lecture - Solutions. [pptx, pdf]
Lecture 13 - Programmable Logic Memories. Part 1. [pptx, pdf]
- RAM HDL Coding Techniques
- Initializing RAM Contents
- ROM HDL Coding Techniques
- 7 Series FPGAs Memory Resources: User Guide - Chapter 1: Block RAM Resources
- 7 Series FPGAs Configurable Logic Block: User Guide - Chapter 2: Functional Details: Distributed RAM
Lecture 12 - Modeling of Circuits with Regular Structure. [pptx, pdf]
Lecture 11 - Review for the Midterm Exam. [pptx, pdf]
Lecture 10 - Finite State Machines. State Diagrams, Algorithmic State Machine (ASM) Charts, and VHDL Code. [pptx, pdf]
Lecture 9 - Introduction to Lab 4. The LightsOut Puzzle. [pptx, pdf]
Lecture 8 - Introduction to Basys 3. Using Seven-Segment Displays, LEDs, Switches, and Buttons. [pptx, pdf]
Lecture 7b - Sequential-Circuit Building Blocks - Part 2. Mixing Description Styles. [pptx, pdf]
Lecture 7a - Sequential Logic Refresher Quiz. [pptx, pdf]
Lecture 6 - Sequential-Circuit Building Blocks - Part 1. Timing Analysis. [pptx, pdf]
Lecture 5 - Combinational-Circuit Building Blocks - Part 2. [pptx, pdf]
Lecture 4 - Combinational-Circuit Building Blocks - Part 1. [pptx, pdf]
Lecture 3 - Examples of Testbenches [pptx, pdf]
Lecture 2 - Introduction to Testbenches [pptx, pdf]
Lecture 2 - HDL Refresher Quiz [pptx, pdf]
Lecture 1 - Objectives, Scope, and Organization of the Course [pptx, pdf]
Posted gradually, typically one day before a given lecture.
See Course Webpage from Spring 2021 for slides from one of the previous years.
Homework 1 - due Sunday, May 14, 11:59pm
Homework 2 - due Sunday, May 14, 11:59pm
- specification - 1 week
- milestone 1 - 2 weeks
- milestone 2 - 2 weeks
- final report & deliverables - 1 week.
Please submit all solutions using Blackboard.
Lab Assignment 6: The LightsOut Puzzle with the Display on a Monitor Screen
Lab Assignment 5: Using an FPro SoC with Standard and Custom Hardware IP Cores: Fast Sorting. (revised on April 8, 2023)
Lab Assignment 4: The LightsOut Puzzle.
Lab Assignment 3: Implementing and Synthesizing Sequential Logic in VHDL.
Lab Assignment 2: Implementing and Synthesizing Combinational Logic in VHDL.
Lab Assignment 1: Developing and Using Effective Testbenches.
The specifications of lab assignments will be posted gradually here on the days when each lab assignment is introduced for the first time (typically Fridays).
Lab Lecture 6: Implementing the LightsOut Puzzle with the display on a monitor screen.
Lab Lecture 5: Developing an FPro SoC with standard & custom hardware IP cores.
Lab Lecture 3: Implementing and Synthesizing Sequential Logic in VHDL.
Lab Lecture 2: Implementing and Synthesizing Combinational Logic in VHDL.
Lab Lecture 1: Developing Effective Testbenches. Simulation using Xilinx Vivado Simulator.
Lab slides and examples will be posted gradually here on the days when each lab assignment is introduced for the first time (typically Fridays).
FREE versions can be installed on your laptops and home workstations.
- Xilinx Vivado
- Xilinx Vitis
- Instructions on how to install Xilinx Vivado
VHDL
VHDL Instructions: Templates & Examples
The Low Carb VHDL Tutorial - by Bryan Mealy
Frequently Asked Questions And Answers about VHDL (Part 1): General from comp.lang.vhdl
Frequently Asked Questions And Answers about VHDL (Part 4): VHDL Glossary from comp.lang.vhdl
C
Top 10 C Language resources that will turn you into a better programmer
Past Lab Exams
Past Midterm Exams for the Lecture
Past Final Exams
Final Exam from Spring 2021 Exam
Final Exam from Spring 2020 Exam
Final Exam from Spring 2019 Group 1 Group 2
Final Exam from Spring 2015: Part 1, Part 2
Final Exam from Spring 2014: Part 1, Part 2
Final Exam from Spring 2013: Part 1, Part 2
Solutions: Part 1, Part 2
Final Exam from Spring 2012 Final Exam Part I - Group 1 Final Exam Part I - Group 2 Final Exam Part II
Solutions: P1_1.jpg, P1_2.jpg, P2.jpg, P3_Task1_1.jpg, P3_Task1_2.jpg, P3_Task2.pdf
Final Exam from Spring 2011 Final Exam Part I - Group 1
Final Exam Part I - Group 2
Final Exam Part II Solutions: P1_Block_diagram.jpg, P2_ASM_chart.jpg, P3_PicoBlaze_program.jpg