-------------------------------------------------------------------------------
-- Title       : Systolic Multiplier
-- Design      : systolic_mult
-- Author      : Brian Loop
-- Company     : George Mason University
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity systolic_mult is
generic ( k:integer:=8);
    port(
     rst : in std_logic;
     a : in std_logic_vector(k-1 downto 0);
     x : in std_logic;
     clk : in std_logic;
     product : out std_logic);
end systolic_mult;

architecture Behavioral of systolic_mult is
    component systolic_block 
    port(
        rst : in std_logic;
        a : in std_logic;
        x : in std_logic;
        clk : in std_logic;
        cin : in std_logic;
        x_out : out std_logic;
        sum : out std_logic);
    end component;
    
     signal sum: std_logic_vector(k downto 0);
     signal x_sig: std_logic_vector(k downto 0);
             
begin

    x_sig(0) <= x;
    sum(k) <= '0';
    product <= sum(0);

   U1:for I in k-1 downto 0 generate
    UN: systolic_block 
        port map(
            rst=> rst,
            a => a(I),
            x => x_sig(I),
            clk =>clk,
            cin => sum(I+1),
            x_out => x_sig(I+1),
            sum => sum(I));
    end generate;
    
    
end Behavioral;