-------------------------------------------------------------------------------
-- Title       : Averaging Circuit Test Bench
-- Design      : AVG
-- Author      : Ambarish Vyas
-- Company     : George Mason University
-------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY avg_tb IS
END avg_tb;

ARCHITECTURE tb_architecture OF avg_tb IS

	-----------------------------------------------------
	--SIGNALs mapped to the input ports of tested entity
	------------------------------------------------------
	
	SIGNAL clk : STD_LOGIC;
	SIGNAL reset : STD_LOGIC;
	SIGNAL first : STD_LOGIC;
	SIGNAL v : STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL x : STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL y : STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL z : STD_LOGIC_VECTOR(3 DOWNTO 0);
	
	------------------------------------------------------
	--SIGNALs mapped to the output ports of tested entity
	------------------------------------------------------
	
	SIGNAL average : STD_LOGIC_VECTOR(3 DOWNTO 0);
	
	--------------------------
	-- State of the circuit
	--------------------------
	TYPE current_state IS (initialize,calculating,done);
	SIGNAL state : current_state;

	------------------------------------
	-- Record Field for inputs
	------------------------------------
	
	TYPE test_vector IS RECORD
		first : STD_LOGIC;
		v 	: STD_LOGIC_VECTOR(3 DOWNTO  0);
		x 	: STD_LOGIC_VECTOR(3 DOWNTO  0);
		y	: STD_LOGIC_VECTOR(3 DOWNTO  0);
		z	: STD_LOGIC_VECTOR(3 DOWNTO  0);
	END RECORD;
	
	---------------------------------------------------------------------
	-- Array of Input Stimuli which calculates an average of 16 numbers 
	---------------------------------------------------------------------

	----------------------------------------------------------------------
	-- Using the given inputs expected sum is 160 and average output is 6
	----------------------------------------------------------------------
	TYPE test_vectors IS ARRAY (0 TO 4) OF test_vector;

	CONSTANT test_vector_table: test_vectors :=( 
	 (first => '1', v => x"A", x => x"F", y => x"0", z => x"1"),
	 (first => '0', v => x"0", x => x"7", y => x"8", z => x"2"),
	 (first => '0', v => x"0", x => x"D", y => x"A", z => x"9"),
	 (first => '0', v => x"0", x => x"0", y => x"B", z => x"0"),
	 (first => '0', v => x"0", x => x"5", y => x"3", z => x"2"));
	 

BEGIN

	-- Unit Under Test port map
	UUT : ENTITY work.avg
		PORT MAP (
			v => v,
			x => x,
			y => y,
			z => z,
			clk => clk,
			reset => reset,
			first => first,
			average => average
		);	 
		
	clock_generator:PROCESS
						BEGIN
						clk <= '0';
						WAIT FOR 5 NS;
						clk  <= '1';
						WAIT FOR 5 NS;
						END PROCESS clock_generator; 
	
	input_stimulus:PROCESS
						BEGIN	
						-------------------------------
						--Reset
						-------------------------------
						reset<= '1';
						state<= initialize;
						
						WAIT FOR 10 NS;
						
						reset <= '0';
					   
						WAIT FOR 10 NS;
						
						----------------------------------------
						-- Give Inputs to the Design Under Test
						-----------------------------------------
						state<= calculating;
						
						FOR i IN 0 TO 4 LOOP
						
					   first <= test_vector_table(i).first;
						v <= test_vector_table(i).v;
						x <= test_vector_table(i).x;
						y <= test_vector_table(i).y;
						z <= test_vector_table(i).z;
						
						WAIT FOR 10 NS;
						
						END LOOP;
						
						state<= done;
			
						WAIT;
		
						END PROCESS input_stimulus;
	
END tb_architecture;