----------------------------------------------------------------------------------
-- Design Name: 	 Midterm_S12 (Secion-203)
-- Module Name:	 MidTerm_203_TB - arch_TB 
-- Target Devices: Spartan-3E
-- Tool versions:  ISE-13.2

-- Malik Umar Sharif 
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;	
use ieee.numeric_std.all;
 
entity Midterm_203_TB is
end Midterm_203_TB;
 
architecture behavior of Midterm_203_TB is 
 
   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal start : std_logic := '0';
	signal A : std_logic_vector(3 downto 0) := "1011";
   signal B : std_logic_vector(3 downto 0) := "1101";

 	--Outputs
   signal P : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 20 ns;
	
begin
 
	-- Instantiate the Unit Under Test (UUT)
	uut : entity work.Midterm_203
	port map
	(
		clk  	=> clk,
		rst 	=> rst,
		start	=> start,
		A		=> A,
		B		=> B,
		P		=> P
	);

	-- Clock generation
	clk <= not clk after clk_period/2;
 
   -- Stimulus Input: Control and Input signals mapped to Unit under test
	Provide_Input : process
   begin		
		
		rst <= '1';
		wait for clk_period;
		rst <= '0';
		wait for clk_period;
		start <= '1';
		
		--------------------------
		-- wait for actual output
		--------------------------
		for i in 0 to 8 loop
			wait until falling_edge(clk);
		end loop;
		
		-------------------------------------------------
		-- Compare actual output with the expected output
		-------------------------------------------------	
		if P /= x"8F" then
			report "Multiplication unsuccessful";
		else
			report "Multiplication successful";
		end if;

      wait;
   end process;

end;