--=====================================
-- Testbench for Midterm - Thursday 2013
-- Author: Umar Sharif
--=====================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;	
use ieee.numeric_std.all;


entity midterm_thursday_TB is
end midterm_thursday_TB;

architecture arch_TB of midterm_thursday_TB is
	
	-- Input signals
	signal din : std_logic_vector(3 downto 0) := "1010"; 
	signal zin : std_logic_vector(7 downto 0) := "01011101"; 
	
	signal clk   : std_logic := '0';
	constant clk_period : time := 10 ns;
	
	signal rst   : std_logic := '1';
	constant rst_width : time := 50 ns;
		
	signal init : std_logic := '0';
	
	-- Output signals 
	signal quotient_actual : std_logic_vector(3 downto 0);
	constant quotient_expected : std_logic_vector(3 downto 0) := "1001";
	
	signal remainder_actual : std_logic_vector(3 downto 0);
	constant remainder_expected : std_logic_vector(3 downto 0) := "0011";
	
	-- State of the circuit
	type current_state is (idle, processing);
	signal state : current_state;
	
begin

	-- Unit Under Test
	UUT : entity work.midterm_thursday
	port map 
	( 
		clk  		=> clk,
		rst  		=> rst, 
		din  	 	=> din,
		zin			=> zin,
		init 		=> init,
		quotient	=> quotient_actual,
		remainder	=> remainder_actual		
	);
	
	-- Clock generation
	clk <= not clk after clk_period/2;
	
	-- Reset generation
	rst_gen: process
	begin
		wait for rst_width;
		rst <= '0';
		wait;
	end process;

	-- Stimulus Input: Control and Input signals mapped to Unit under test
	Provide_Input : process
	
	variable error_count : integer := 0;
	
	begin	
		wait for rst_width;	-- wait for reset to be low
		
		-----------------------------
		-- Idle state : No encryption
		-----------------------------
		wait until falling_edge(clk);
		state 		<= idle;
		init 	 	<= '1'; 
		wait for clk_period;
		init 	 	<= '0';
		
		--------------
		-- processing
		--------------
		state 		<= processing;
		wait for clk_period*4;
		
		-------------------------------------------------
		-- Compare actual output with the expected output
		-------------------------------------------------
		if ( quotient_actual /= quotient_expected ) then 
			error_count := error_count + 1;
		end if;
		
		if ( remainder_actual /= remainder_expected ) then 
			error_count := error_count + 1;
		end if;
			
		if error_count /= 0 then 
			report "Division unsuccessful";
		else 
			report "Division successful";
		end if;
		
		wait for clk_period*2;
		
		assert false
		report "Simulation Completed" 
		severity failure;

	end process;
		
end arch_TB;