--====================
-- LFSR component
-- Author: Umar Sharif
--====================

library ieee;
use ieee.std_logic_1164.all;

entity lfsr is
	generic (
				N : integer := 8
			);
    port ( 
			-- inputs
			clk 	:	in 	std_logic;
			rst		:	in 	std_logic;
			en		:	in 	std_logic;
			ld		:	in 	std_logic;
			IV		: 	in	std_logic_vector(N-1 downto 0);
			C 		: in std_logic_vector(1 to N);
			
			-- outputs
			lfsr_out	: 	out  std_logic_vector (N-1 downto 0)
		); 
end lfsr;

architecture behavioral of lfsr is

	-- intermediate signals  
	signal  Q_fb : std_logic;	-- feedback signal
	signal  Q : std_logic_vector (N-1 downto 0); 
	
begin
	
	process (C, Q)
	begin
		if (N = 8) then
			-- feedback from all the taps of LFSR
			Q_fb <= 	(C(1) and Q(7)) xor
						(C(2) and Q(6)) xor
						(C(3) and Q(5)) xor
						(C(4) and Q(4)) xor
						(C(5) and Q(3)) xor
						(C(6) and Q(2)) xor
						(C(7) and Q(1)) xor
						(C(8) and Q(0));
		
		elsif (N = 4) then
			-- feedback from all the taps of LFSR
			Q_fb <= 	(C(1) and Q(3)) xor
						(C(2) and Q(2)) xor
						(C(3) and Q(1)) xor
						(C(4) and Q(0));
		end if;
	end process;
	
	-- load or shifting value inside LFSR
	ld_shft_D_FFs: process (rst, clk)
	begin
		if (rst = '1') then
			Q <= (others => '0');
		elsif rising_edge(clk) then
			if(en = '1') then
				if(ld = '1') then
					Q <= IV;					-- load IV
				else
					Q <= Q_fb & Q(N-1 downto 1);	-- shift operation
				end if;
			end if;	
		end if;
	end process;
	
	lfsr_out <= Q;
end behavioral;