--=====================================
-- Testbench for Midterm - Thursday 2013
-- Author: Umar Sharif
--=====================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;	
use ieee.numeric_std.all;


entity midterm_wednesday_TB is
end midterm_wednesday_TB;

architecture arch_TB of midterm_wednesday_TB is
	
	-- Input signals
	signal IV1 : std_logic_vector(7 downto 0) := x"75";
	signal IV2 : std_logic_vector(3 downto 0) := x"E";
	signal IV3 : std_logic_vector(3 downto 0) := x"A";
	signal init : std_logic := '0';
	
	constant MESSAGE : std_logic_vector(14 downto 0) := "111111011011100"; 

	-- Output signals 
	signal CIPHERTEXT_ACTUAL : std_logic_vector(14 downto 0);
	constant CIPERTEXT_EXPECTED : std_logic_vector(14 downto 0) := "110001001000100";
	
	signal clk   : std_logic := '0';
	constant clk_period : time := 6.7 ns;
	
	signal rst   : std_logic := '1';
	constant rst_width : time := 100 ns;
	
	-- State of the circuit
	type current_state is (Idle, init_state, processing);
	signal state : current_state;
	
begin

	-- Unit Under Test
	UUT : entity work.midterm_wednesday
	port map 
	( 
		clk  		=> clk,
		rst  		=> rst,
		IV1  	 	=> IV1,
		IV2  	 	=> IV2,
		IV3  	 	=> IV3,
		init		=> init,
		MESSAGE		=> MESSAGE,
	
		-- outputs
		CIPHERTEXT	=> CIPHERTEXT_ACTUAL
	);
	
	-- Clock generation
	clk <= not clk after clk_period/2;
	
	-- Reset generation
	rst_gen: process
	begin
		wait for rst_width;
		rst <= '0';
		wait;
	end process;

	-- Stimulus Input: Control and Input signals mapped to Unit under test
	Provide_Input : process
	
	variable error_count : integer := 0;
	
	begin	
		wait for rst_width;	-- wait for reset to be low
		
		-----------------------------
		-- Idle state : No encryption
		-----------------------------
		wait until falling_edge(clk);
		state 	<= Idle;
		init	<= '0';	
		
		-------------------------------------
		-- init (active for one clock period)
		-------------------------------------
		wait until falling_edge(clk);
		state 	<= init_state;
		init	<= '1';	
		wait for clk_period;
		init 	<= '0';
		
		--------------
		-- Processing
		--------------
		state 	<= processing;
		wait for clk_period * 16;
		
		---------------------------------------------
		-- Compare actual output with the expected output
		---------------------------------------------
		if ( CIPHERTEXT_ACTUAL /= CIPERTEXT_EXPECTED ) then 
			error_count := error_count + 1;
		end if;
		
		if error_count = 0 then 
			report "Encryption successful";
		else 
			report "Encryption unsuccessful";
		end if;
		
		wait for 2 * clk_period;
		
		assert false
		report "Simulation Completed" 
		severity failure;

	end process;
		
end arch_TB;