--====================
-- LFSR component
-- Author: Umar Sharif
--====================

library ieee;
use ieee.std_logic_1164.all;

entity lfsr is
	generic (
				C : in std_logic_vector(3 downto 0) := "0001"
			);
    port ( 
			-- inputs
			clk 		:	in 	std_logic;
			rst		:	in 	std_logic;
			en			:	in 	std_logic;
			ld			:	in 	std_logic;
			D			: 	in		std_logic_vector(3 downto 0);			
			-- outputs
			Sout		: 	out 	std_logic
		); 
end lfsr;

architecture behavioral of lfsr is

	-- intermediate signals  
	signal  Q_fb : std_logic;	-- feedback signal
	signal  Q : std_logic_vector (3 downto 0); 
	
begin
	
	-- feedback from all the taps of LFSR
Q_fb <= 	(C(3) and Q(3)) xor
			(C(2) and Q(2)) xor
			(C(1) and Q(1)) xor
			(C(0) and Q(0));
	
	-- load or shifting value inside LFSR
	ld_shft_D_FFs: process (rst, clk)
	begin
		if (rst = '1') then
			Q <= (others => '0');
		elsif rising_edge(clk) then
			if(en = '1') then
				if(ld = '1') then
					Q <= D;					-- load IV
				else
					Q <= Q_fb & Q(3 downto 1);	-- shift operation
				end if;
			end if;	
		end if;
	end process;
	
	Sout <= Q(0);
end behavioral;