library ieee;
use ieee.std_logic_1164.all; 

entity regn is
	generic (N : integer := 4);
	port ( 	  
			clk 	: in std_logic;
			rst 	: in std_logic;
			en 		: in std_logic; 
			input  	: in std_logic_vector(N-1 downto 0);
			output 	: out std_logic_vector(N-1 downto 0)
	);
end regn;

architecture struct of regn is

-- intermediate signals
signal output_sig : std_logic_vector(N-1 downto 0);

begin	

	gen : process( clk, rst )
	begin
		if ( rst = '1' ) then
			output_sig <= (others => '0');
		elsif rising_edge( clk ) then
			if ( en = '1' ) then
				output_sig <= input;
			end if;
		end if;
	end process;

	output <= output_sig;
	

end struct;