library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY controller IS
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
a : IN STD_LOGIC;
b : IN STD_LOGIC;
x : OUT STD_LOGIC;
y : OUT STD_LOGIC;
z : OUT STD_LOGIC);
END controller;
ARCHITECTURE mixed OF controller IS
TYPE FSM_state IS (S0, S1, S2, S3, S4);
SIGNAL State: FSM_state;
BEGIN
FSM: PROCESS (clk, rst)
BEGIN
IF(rst = '1') THEN
State <= S0;
ELSIF rising_edge(clk) THEN
CASE State IS
WHEN S0 =>
IF a = '1' THEN
State <= S1;
ELSE
State <= S0;
END IF;
WHEN S1 =>
State <= S2;
WHEN S2 =>
IF a = '1' THEN
State <= S3;
ELSE
State <= S4;
END IF;
WHEN S3 =>
IF b = '1' THEN
State <= S4;
ELSE
State <= S2;
END IF;
WHEN S4 =>
IF a = '1' THEN
State <= S1;
ELSIF b = '1' THEN
State <= S3;
ELSE
State <= S0;
END IF;
END CASE;
END IF;
END PROCESS;
x <= '1' WHEN (State = S1 and a='0') OR (State = S2 and a='1') OR
(State = S4 and a='0') ELSE
'0';
y <= '1' WHEN (State = S2) OR (State = S3 and b='1') OR ( State = S4 ) ELSE
'0';
z <= '1' WHEN (State = S1 and a='0') OR (State = S2 and a='0') OR
(State = S3 and b='0') OR
(State = S4 and a='0' and b='1') ELSE
'0';
END mixed;