LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS
   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal din : std_logic_vector(3 downto 0) := (others => '0');
   signal go : std_logic := '0';
   signal dout_mode : std_logic_vector(1 downto 0) := (others => '0');

 	--Outputs
   signal done : std_logic;
   signal dout : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: entity work.Statistics(Structure)
   PORT MAP (
          clk   => clk,
          reset => reset,
          din   => din,
          go    => go,
          dout_mode => dout_mode,
          done => done,
          dout => dout
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
      reset <= '1';
		wait for clk_period;
		reset <= '0';

		go <= '1';

		for i in 0 to 7 loop
			din <= din + 1;
			wait for clk_period;
		end loop;

		go<='0';
		wait until done = '1';

		dout_mode <= "01";
		wait for clk_period;
		dout_mode <= "10";
		wait for clk_period;
		dout_mode <= "11";
		wait for clk_period;

      wait;
   end process;

END behavior;