----------------------------------------------------------------------------------
-- Controller
-- Name : Tatiana Rodriguez 
-- Class: ECE 448-204
-- School: George Mason University
-- Created on 03/15/16 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;


entity Controller is
    Port ( Clock : in  STD_LOGIC;
           Resetn : in  STD_LOGIC;
           S : in  STD_LOGIC;
           AgtB : in  STD_LOGIC;
           zi : in  STD_LOGIC;
           zj : in  STD_LOGIC;
           Wr : out  STD_LOGIC;
           Li : out  STD_LOGIC;
           Ei : out  STD_LOGIC;
           Lj : out  STD_LOGIC;
           Ej : out  STD_LOGIC;
           EA : out  STD_LOGIC;
           EB : out  STD_LOGIC;
           Bout : out  STD_LOGIC;
           Csel : out  STD_LOGIC;
           Done : out STD_LOGIC);
end Controller;

architecture Behavioral of Controller is
	type state is (S0, S1, S2, S3, S4, S5, S6, S7);
	signal y : state;
begin
	process(clock, resetn)
	begin
				if ( resetn = '1') then 
					y <= S0;
				elsif rising_edge (clock) then
					case y is 
						when S0 => 
							if (S = '1') then 
								y <= S1;
							else
								y  <= S0;
							end if;
						when S1 =>
							y <= S2;
						when S2 =>
							y <= S3;
						when S3 =>
							if (AgtB = '1') then 
								y <= S4;
							else
								if (zj = '1') then 
									if (zi = '1') then 
										y <= S7;
									else
										y <= S1;
									end if;
								else
									y <= S2;
								end if;
							end if;
						when S4 =>
							y <= S5;
						when S5 =>
							y <= S6;
						when S6 =>
							if (zj = '1') then 
								if (zi = '1') then 
									y <= S7;
								else
									y <= S1;
								end if;
							else
								y <= S2;
							end if;
						when S7 =>
							 if (s = '0') then 
								y <= S0;
							else 
								y <= S7;
							end if;
					end case;
				end if;
			end process;
							
  -- Outputs 
			  Wr <= '1' when ((y = S4) or (y = s5)) else '0';
           Li <= '1' when (y = S0) else '0';
           Ei <= '1' when ((y = S0) or ((Y = S3) and (AgtB = '0') and (zj = '1') and (zi = '0')) or ((Y = S6) and (zj = '1') and (zi = '0'))) else '0';
           Lj <= '1' when (y = S1) else '0';
           Ej <= '1' when ((y = S1) or ((y = S3) and (AgtB = '0') and (zj = '0')) or ((y = S6) and zj = '0')) else '0';
           EA <= '1' when ((y = S1) or (y = S6));
           EB <= '1' when (y = S2) else '0';
           Bout <= '1' when (y = S4) else '0';
           Csel <= '1' when (y = S2) else '0';
           Done <= '1' when (y = S7) else '0';

end Behavioral;