----------------------------------------------------------------------------------
-- DataPath
-- Name : Tatiana Rodriguez 
-- Class: ECE 448-204
-- School: George Mason University
-- Created on 03/15/16 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;


entity DATAPATH is
	Generic ( N : integer := 32;
				 L : integer := 6);
    Port ( DataIn : in  STD_LOGIC_VECTOR (N-1 downto 0);
           Raddr : in  STD_LOGIC_VECTOR (L-1 downto 0);
           WrInit : in  STD_LOGIC;
           Rd : in  STD_LOGIC;
			  S : in  STD_LOGIC;
           Clock : in  STD_LOGIC;
           Resetn : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Li : in  STD_LOGIC;
           Ei : in  STD_LOGIC;
			  Lj : in  STD_LOGIC;
           Ej : in  STD_LOGIC;
           EA : in  STD_LOGIC;
           EB : in  STD_LOGIC;
           Bout : in  STD_LOGIC;
           Csel : in  STD_LOGIC;
           AgtB : out  STD_LOGIC;
           Zi : out  STD_LOGIC;
           Zj : out  STD_LOGIC;
           DataOut : out  STD_LOGIC_VECTOR (N-1 downto 0));
end DATAPATH;

architecture Behavioral of DATAPATH is
	signal We: STD_LOGIC;
	signal i, j, muxc, Addr, count : STD_LOGIC_VECTOR(L-1 downto 0);
	signal Mij, A, B , Din, ABMux: STD_LOGIC_VECTOR(N-1 downto 0);
	
	constant zero : STD_LOGIC_VECTOR( L-1 downto 0) := (others => '0');
	constant load : STD_LOGIC := '1';
	constant K : integer := 6;
	

begin
			--Register 1 with load zero
			reg1: entity work.Reg(Behavioral)
					generic map ( N => L)
					 Port map ( Din => zero,
								  LD => Li,
								  EN => Ei,
								  CLK => clock,
								  RST => not(Resetn),
								  Dout => i );
			-- Zi
			zi <= '1' when i = (k-2) else '0';
			--Counter
			count <= i + 1;
			counter: entity work.Reg(Behavioral)
					generic map ( N => L)
					 Port map ( Din => count,
								  LD => Lj,
								  EN => Ej,
								  CLK => clock,
								  RST => not(Resetn),
								  Dout => j );
			 -- zj
			zj <= '1' when j = (K-1) else '0';
			
			-- mux with Csel
			MuxC <= j when (Csel = '1') else i;
			
			--mux with Radd
			Addr<= MuxC when (s = '1') else Raddr;
			
			--RAM 
			RAM1 : entity work.ram(behavioral)
						 generic map ( w =>N, -- number of bits per RAM word
									      r => L) -- 2^r = number of words in RAM 
						  port map (clk => clock, 
									  we  => we,  
									  a   =>Addr,  
									  di  => Din,  
									  do  => Mij
									  ); 
		 -- BUFFER
		 DATAOut <= Mij when (RD = '1') else (others => 'Z');
		
		 -- reg A
		 Reg_A : entity work.Reg(Behavioral)
					generic map ( N => N)
					 Port map ( Din => Mij,
								  LD => Load,
								  EN => EA,
								  CLK => clock,
								  RST => not(Resetn),
								  Dout => A );
		-- reg B
		 Reg_B : entity work.Reg(Behavioral)
					generic map ( N => N)
					 Port map ( Din => Mij,
								  LD => Load,
								  EN => EB,
								  CLK => clock,
								  RST => not(Resetn),
								  Dout => B );
		-- Agtb
		AgtB <= '1' when (A > B) else '0';
		
		-- ABMux
		ABMux <= A when (Bout = '0') else B;
		
		-- we 
		We <= WrInit or Wr;
		
		-- Din mux
		Din <= ABMux when (S = '1') else DataIn;
								  
					
			

end Behavioral;