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-- Register 
-- Name : Tatiana Rodriguez 
-- Class: ECE 448-204
-- School: George Mason University
-- Created on 03/15/16 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

entity Reg is
	generic ( N : integer := 5);
    Port ( Din : in  STD_LOGIC_VECTOR (N-1 downto 0);
           LD : in  STD_LOGIC;
           EN : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           Dout : out  STD_LOGIC_VECTOR (N-1 downto 0));
end Reg;

architecture Behavioral of Reg is
		signal q : STD_LOGIC_VECTOR( N-1 downto 0);
begin
	process(clk, rst)
	begin
			if rst = '1' then 
				q <= (others => '0');
			elsif rising_edge(clk) then 
				if en = '1' then 
					if LD = '1' then 
						q <= Din;
					end if;
				end if;
			end if;
	end process;

end Behavioral;