---------------------------------------------------------------------------------- -- Sort -- Name : Tatiana Rodriguez -- Class: ECE 448-204 -- School: George Mason University -- Created on 03/15/16 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; entity Sort is Generic ( N : integer := 32; L : integer := 6 ); Port ( Clock : in STD_LOGIC; resetn : in STD_LOGIC; DataIn : in STD_LOGIC_VECTOR (N- 1 downto 0); Radd : in STD_LOGIC_VECTOR (L- 1 downto 0); WrInit : in STD_LOGIC; S : in STD_LOGIC; Rd : in STD_LOGIC; DataOut : out STD_LOGIC_VECTOR (N-1 downto 0); Done : out STD_LOGIC); end Sort; architecture Behavioral of Sort is signal AgtB, zi, zj, Wr, Li, Ei, Lj, Ej : STD_LOGIC; signal EA, EB, Bout, Csel : STD_LOGIC; begin DATAPATH1 : entity work.DATAPATH(Behavioral) Generic map ( N => N, L => L) Port map ( DataIn => DataIn, Raddr => Radd, WrInit => WrInit, Rd => Rd, S => S, Clock => clock, Resetn => resetn, Wr => wr, Li => Li, Ei => Ei, Lj => Lj, Ej => Ej, EA => EA, EB => EB, Bout => Bout, Csel => Csel, AgtB => AgtB, Zi => zi, Zj => zj, DataOut => DataOut); controller1: entity work.controller(Behavioral) Port map ( Clock => clock, Resetn => resetn, S => S, AgtB => AgtB, Zi => zi, Zj => zj, Wr => wr, Li => Li, Ei => Ei, Lj => Lj, Ej => Ej, EA => EA, EB => EB, Bout => Bout, Csel => Csel, Done => Done); end Behavioral;