----------------------------------------------------------------------------------
-- Sort testbench
-- Name : Tatiana Rodriguez 
-- Class: ECE 448-204
-- School: George Mason University
-- Created on 03/15/16 
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Sort_tb IS
END Sort_tb;
 
ARCHITECTURE behavior OF Sort_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Sort
    PORT(
         Clock : IN  std_logic;
         resetn : IN  std_logic;
         DataIn : IN  std_logic_vector(31 downto 0);
         Radd : IN  std_logic_vector(5 downto 0);
         WrInit : IN  std_logic;
         S : IN  std_logic;
         Rd : IN  std_logic;
         DataOut : OUT  std_logic_vector(31 downto 0);
         Done : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Clock : std_logic := '0';
   signal resetn : std_logic := '0';
   signal DataIn : std_logic_vector(31 downto 0) := (others => '0');
   signal Radd : std_logic_vector(5 downto 0) := (others => '0');
   signal WrInit : std_logic := '0';
   signal S : std_logic := '0';
   signal Rd : std_logic := '0';

 	--Outputs
   signal DataOut : std_logic_vector(31 downto 0);
   signal Done : std_logic;

   -- Clock period definitions
   constant Clock_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Sort PORT MAP (
          Clock => Clock,
          resetn => resetn,
          DataIn => DataIn,
          Radd => Radd,
          WrInit => WrInit,
          S => S,
          Rd => Rd,
          DataOut => DataOut,
          Done => Done
        );

   -- Clock process definitions
   Clock_process :process
   begin
		Clock <= '0';
		wait for Clock_period/2;
		Clock <= '1';
		wait for Clock_period/2;
   end process;
 
	reset_process: process
	begin 
		resetn <= '0';
		wait for clock_period *2;
		resetn <= '1';
		wait;
	end process;
   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 20 ns.
      wait for 20 ns;	
		
		for i in 0 to 4 loop
		DataIn <= x"00000000" + i;
      Radd <= "000000" + i;
      WrInit <= '1';
      S <= '0';
      Rd <= '1';
		wait for clock_period;
	   end loop;
		
		for i in 0 to 4 loop
		DataIn <= x"00000000" + i;
      Radd <= "000000" + i;
      WrInit <= '0';
      S <= '1';
      Rd <= '1';
		
		--------------------------
		-- wait for actual output
		--------------------------
			wait until done = '1';
	   end loop;
		
		DataIn <= x"00000000";
      Radd <= "000000";
      WrInit <= '0';
      S <= '1';
      Rd <= '0';
		
		--------------------------
		-- wait for actual output
		--------------------------
			wait until done = '1';
		
	
      wait;
   end process;

END;