----------------------------------------------------------------------------------
-- Designer:       Sanjay Deshpande
-- Create Date:    02:32:04 03/15/2016 
-- Design Name:    ram
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;		
 
entity ram is 	  
  generic ( w : integer := 32; 
            -- number of bits per RAM word
            r : integer := 6); 
            -- 2^r = number of words in RAM 
  port (clk : in std_logic;  
        we  : in std_logic;   
        a   : in std_logic_vector(r-1 downto 0);   
        di  : in std_logic_vector(w-1 downto 0);   
        do  : out std_logic_vector(w-1 downto 0));   
end ram;   

architecture behavioral of ram is   
  type ram_type is array (0 to 2**r-1) 
        of std_logic_vector (w-1 downto 0);   
  signal RAM : ram_type := (others => (others => '0'));   
begin   
  process (clk)   
  begin   
    if rising_edge(clk) then   
      if (we = '1') then   
        RAM(to_integer(unsigned(a))) <= di;   
      end if;   
    end if;   
  end process;   
  do <= RAM(to_integer(unsigned(a)));   
end behavioral;