Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 | Date : Wed Mar 6 21:00:22 2019 | Host : HofnerdLaptop running 64-bit unknown | Command : report_utilization -file /home/spencer/School/ece448/labs/LabMidterm/timing_report.txt -name utilization_2 | Design : toplevel | Device : 7a35tcpg236-1 | Design State : Routed ---------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type 2. Slice Logic Distribution 3. Memory 4. DSP 5. IO and GT Specific 6. Clocking 7. Specific Feature 8. Primitives 9. Black Boxes 10. Instantiated Netlists 1. Slice Logic -------------- +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ | Slice LUTs | 65 | 0 | 20800 | 0.31 | | LUT as Logic | 65 | 0 | 20800 | 0.31 | | LUT as Memory | 0 | 0 | 9600 | 0.00 | | Slice Registers | 46 | 0 | 41600 | 0.11 | | Register as Flip Flop | 46 | 0 | 41600 | 0.11 | | Register as Latch | 0 | 0 | 41600 | 0.00 | | F7 Muxes | 0 | 0 | 16300 | 0.00 | | F8 Muxes | 0 | 0 | 8150 | 0.00 | +-------------------------+------+-------+-----------+-------+ 1.1 Summary of Registers by Type -------------------------------- +-------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +-------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 0 | Yes | - | Set | | 46 | Yes | - | Reset | | 0 | Yes | Set | - | | 0 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. Slice Logic Distribution --------------------------- +--------------------------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +--------------------------------------------+------+-------+-----------+-------+ | Slice | 19 | 0 | 8150 | 0.23 | | SLICEL | 14 | 0 | | | | SLICEM | 5 | 0 | | | | LUT as Logic | 65 | 0 | 20800 | 0.31 | | using O5 output only | 0 | | | | | using O6 output only | 50 | | | | | using O5 and O6 | 15 | | | | | LUT as Memory | 0 | 0 | 9600 | 0.00 | | LUT as Distributed RAM | 0 | 0 | | | | LUT as Shift Register | 0 | 0 | | | | Slice Registers | 46 | 0 | 41600 | 0.11 | | Register driven from within the Slice | 45 | | | | | Register driven from outside the Slice | 1 | | | | | LUT in front of the register is unused | 0 | | | | | LUT in front of the register is used | 1 | | | | | Unique Control Sets | 4 | | 8150 | 0.05 | +--------------------------------------------+------+-------+-----------+-------+ * Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. 3. Memory --------- +----------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------+------+-------+-----------+-------+ | Block RAM Tile | 0 | 0 | 50 | 0.00 | | RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | | RAMB18 | 0 | 0 | 100 | 0.00 | +----------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 4. DSP ------ +-----------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------+------+-------+-----------+-------+ | DSPs | 0 | 0 | 90 | 0.00 | +-----------+------+-------+-----------+-------+ 5. IO and GT Specific --------------------- +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ | Bonded IOB | 36 | 1 | 106 | 33.96 | | IOB Master Pads | 18 | | | | | IOB Slave Pads | 17 | | | | | Bonded IPADs | 0 | 0 | 10 | 0.00 | | Bonded OPADs | 0 | 0 | 4 | 0.00 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 | | PHASER_REF | 0 | 0 | 5 | 0.00 | | OUT_FIFO | 0 | 0 | 20 | 0.00 | | IN_FIFO | 0 | 0 | 20 | 0.00 | | IDELAYCTRL | 0 | 0 | 5 | 0.00 | | IBUFDS | 0 | 0 | 104 | 0.00 | | GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | | IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | | ILOGIC | 0 | 0 | 106 | 0.00 | | OLOGIC | 0 | 0 | 106 | 0.00 | +-----------------------------+------+-------+-----------+-------+ 6. Clocking ----------- +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ | BUFGCTRL | 1 | 0 | 32 | 3.13 | | BUFIO | 0 | 0 | 20 | 0.00 | | MMCME2_ADV | 0 | 0 | 5 | 0.00 | | PLLE2_ADV | 0 | 0 | 5 | 0.00 | | BUFMRCE | 0 | 0 | 10 | 0.00 | | BUFHCE | 0 | 0 | 72 | 0.00 | | BUFR | 0 | 0 | 20 | 0.00 | +------------+------+-------+-----------+-------+ 7. Specific Feature ------------------- +-------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------+------+-------+-----------+-------+ | BSCANE2 | 0 | 0 | 4 | 0.00 | | CAPTUREE2 | 0 | 0 | 1 | 0.00 | | DNA_PORT | 0 | 0 | 1 | 0.00 | | EFUSE_USR | 0 | 0 | 1 | 0.00 | | FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | | ICAPE2 | 0 | 0 | 2 | 0.00 | | PCIE_2_1 | 0 | 0 | 1 | 0.00 | | STARTUPE2 | 0 | 0 | 1 | 0.00 | | XADC | 0 | 0 | 1 | 0.00 | +-------------+------+-------+-----------+-------+ 8. Primitives ------------- +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ | FDCE | 46 | Flop & Latch | | LUT3 | 35 | LUT | | LUT2 | 24 | LUT | | IBUF | 19 | IO | | OBUF | 17 | IO | | CARRY4 | 12 | CarryLogic | | LUT6 | 6 | LUT | | LUT4 | 6 | LUT | | LUT1 | 5 | LUT | | LUT5 | 4 | LUT | | BUFG | 1 | Clock | +----------+------+---------------------+ 9. Black Boxes -------------- +----------+------+ | Ref Name | Used | +----------+------+ 10. Instantiated Netlists ------------------------- +----------+------+ | Ref Name | Used | +----------+------+ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 | Date : Wed Mar 6 21:19:27 2019 | Host : HofnerdLaptop running 64-bit unknown | Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 -file /home/spencer/School/ece448/labs/LabMidterm/timing_report.txt -append | Design : toplevel | Device : 7a35t-cpg236 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 18 input ports with no input delay specified. (HIGH) m[0] m[10] m[11] m[12] m[13] m[14] m[15] m[1] m[2] m[3] m[4] m[5] m[6] m[7] m[8] m[9] reset write_m There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 17 ports with no output delay specified. (HIGH) c[0] c[10] c[11] c[12] c[13] c[14] c[15] c[1] c[2] c[3] c[4] c[5] c[6] c[7] c[8] c[9] done There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 2.018 0.000 0 96 0.162 0.000 0 96 4.500 0.000 0 47 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 2.018 0.000 0 92 0.162 0.000 0 92 4.500 0.000 0 47 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** sys_clk_pin sys_clk_pin 7.532 0.000 0 4 0.736 0.000 0 4 ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk_pin (none) sys_clk_pin ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: sys_clk_pin To Clock: sys_clk_pin Setup : 0 Failing Endpoints, Worst Slack 2.018ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.162ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.018ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[7]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 8.022ns (logic 4.710ns (58.716%) route 3.312ns (41.284%)) Logic Levels: 11 (CARRY4=6 LUT2=2 LUT3=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns = ( 14.847 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.155 r DP/w10_carry/CO[3] net (fo=1, routed) 0.000 10.155 DP/w10_carry_n_0 SLICE_X5Y19 r DP/w10_carry__0/CI SLICE_X5Y19 CARRY4 (Prop_carry4_CI_O[0]) 0.222 10.377 r DP/w10_carry__0/O[0] net (fo=1, routed) 0.591 10.967 DP/w10[4] SLICE_X3Y19 r DP/v1d_carry__0_i_4/I0 SLICE_X3Y19 LUT3 (Prop_lut3_I0_O) 0.299 11.266 r DP/v1d_carry__0_i_4/O net (fo=1, routed) 0.000 11.266 DP/v1d_carry__0_i_4_n_0 SLICE_X3Y19 r DP/v1d_carry__0/S[0] SLICE_X3Y19 CARRY4 (Prop_carry4_S[0]_O[3]) 0.606 11.872 r DP/v1d_carry__0/O[3] net (fo=2, routed) 0.960 12.832 DP/read[7] SLICE_X4Y19 r DP/rw_reg_value[7]_i_1/I2 SLICE_X4Y19 LUT3 (Prop_lut3_I2_O) 0.334 13.166 r DP/rw_reg_value[7]_i_1/O net (fo=1, routed) 0.000 13.166 DP/rw_out[7] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 14.847 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[7]/C clock pessimism 0.297 15.144 clock uncertainty -0.035 15.109 SLICE_X4Y19 FDCE (Setup_fdce_C_D) 0.075 15.184 DP/rw_reg_value_reg[7] ------------------------------------------------------------------- required time 15.184 arrival time -13.166 ------------------------------------------------------------------- slack 2.018 Slack (MET) : 2.284ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[4]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 7.755ns (logic 4.594ns (59.237%) route 3.161ns (40.763%)) Logic Levels: 11 (CARRY4=6 LUT2=2 LUT3=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns = ( 14.847 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_O[3]) 0.606 10.229 r DP/w10_carry/O[3] net (fo=1, routed) 0.456 10.684 DP/w10[3] SLICE_X3Y18 r DP/v1d_carry_i_1/I0 SLICE_X3Y18 LUT3 (Prop_lut3_I0_O) 0.306 10.990 r DP/v1d_carry_i_1/O net (fo=1, routed) 0.000 10.990 DP/v1d_carry_i_1_n_0 SLICE_X3Y18 r DP/v1d_carry/S[3] SLICE_X3Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 11.391 r DP/v1d_carry/CO[3] net (fo=1, routed) 0.000 11.391 DP/v1d_carry_n_0 SLICE_X3Y19 r DP/v1d_carry__0/CI SLICE_X3Y19 CARRY4 (Prop_carry4_CI_O[0]) 0.235 11.626 r DP/v1d_carry__0/O[0] net (fo=2, routed) 0.944 12.571 DP/read[4] SLICE_X4Y19 r DP/rw_reg_value[4]_i_1/I2 SLICE_X4Y19 LUT3 (Prop_lut3_I2_O) 0.329 12.900 r DP/rw_reg_value[4]_i_1/O net (fo=1, routed) 0.000 12.900 DP/rw_out[4] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 14.847 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[4]/C clock pessimism 0.297 15.144 clock uncertainty -0.035 15.109 SLICE_X4Y19 FDCE (Setup_fdce_C_D) 0.075 15.184 DP/rw_reg_value_reg[4] ------------------------------------------------------------------- required time 15.184 arrival time -12.900 ------------------------------------------------------------------- slack 2.284 Slack (MET) : 2.301ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[5]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 7.704ns (logic 4.709ns (61.125%) route 2.995ns (38.875%)) Logic Levels: 11 (CARRY4=6 LUT2=2 LUT3=3) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.260ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_O[3]) 0.606 10.229 r DP/w10_carry/O[3] net (fo=1, routed) 0.456 10.684 DP/w10[3] SLICE_X3Y18 r DP/v1d_carry_i_1/I0 SLICE_X3Y18 LUT3 (Prop_lut3_I0_O) 0.306 10.990 r DP/v1d_carry_i_1/O net (fo=1, routed) 0.000 10.990 DP/v1d_carry_i_1_n_0 SLICE_X3Y18 r DP/v1d_carry/S[3] SLICE_X3Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 11.391 r DP/v1d_carry/CO[3] net (fo=1, routed) 0.000 11.391 DP/v1d_carry_n_0 SLICE_X3Y19 r DP/v1d_carry__0/CI SLICE_X3Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 11.739 r DP/v1d_carry__0/O[1] net (fo=2, routed) 0.778 12.517 DP/read[5] SLICE_X0Y19 r DP/rw_reg_value[5]_i_1/I2 SLICE_X0Y19 LUT3 (Prop_lut3_I2_O) 0.331 12.848 r DP/rw_reg_value[5]_i_1/O net (fo=1, routed) 0.000 12.848 DP/rw_out[5] SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.508 14.849 DP/CLK SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[5]/C clock pessimism 0.260 15.109 clock uncertainty -0.035 15.074 SLICE_X0Y19 FDCE (Setup_fdce_C_D) 0.075 15.149 DP/rw_reg_value_reg[5] ------------------------------------------------------------------- required time 15.149 arrival time -12.848 ------------------------------------------------------------------- slack 2.301 Slack (MET) : 2.458ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[6]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 7.582ns (logic 4.645ns (61.263%) route 2.937ns (38.737%)) Logic Levels: 11 (CARRY4=6 LUT2=2 LUT3=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns = ( 14.847 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.155 r DP/w10_carry/CO[3] net (fo=1, routed) 0.000 10.155 DP/w10_carry_n_0 SLICE_X5Y19 r DP/w10_carry__0/CI SLICE_X5Y19 CARRY4 (Prop_carry4_CI_O[0]) 0.222 10.377 r DP/w10_carry__0/O[0] net (fo=1, routed) 0.591 10.967 DP/w10[4] SLICE_X3Y19 r DP/v1d_carry__0_i_4/I0 SLICE_X3Y19 LUT3 (Prop_lut3_I0_O) 0.299 11.266 r DP/v1d_carry__0_i_4/O net (fo=1, routed) 0.000 11.266 DP/v1d_carry__0_i_4_n_0 SLICE_X3Y19 r DP/v1d_carry__0/S[0] SLICE_X3Y19 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 11.813 r DP/v1d_carry__0/O[2] net (fo=2, routed) 0.585 12.398 DP/read[6] SLICE_X4Y19 r DP/rw_reg_value[6]_i_1/I2 SLICE_X4Y19 LUT3 (Prop_lut3_I2_O) 0.328 12.726 r DP/rw_reg_value[6]_i_1/O net (fo=1, routed) 0.000 12.726 DP/rw_out[6] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 14.847 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C clock pessimism 0.297 15.144 clock uncertainty -0.035 15.109 SLICE_X4Y19 FDCE (Setup_fdce_C_D) 0.075 15.184 DP/rw_reg_value_reg[6] ------------------------------------------------------------------- required time 15.184 arrival time -12.726 ------------------------------------------------------------------- slack 2.458 Slack (MET) : 2.957ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 7.038ns (logic 4.390ns (62.374%) route 2.648ns (37.626%)) Logic Levels: 10 (CARRY4=5 LUT2=2 LUT3=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns = ( 14.847 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 10.047 r DP/w10_carry/O[1] net (fo=1, routed) 0.304 10.351 DP/w10[1] SLICE_X3Y18 r DP/v1d_carry_i_3/I0 SLICE_X3Y18 LUT3 (Prop_lut3_I0_O) 0.303 10.654 r DP/v1d_carry_i_3/O net (fo=1, routed) 0.000 10.654 DP/v1d_carry_i_3_n_0 SLICE_X3Y18 r DP/v1d_carry/S[1] SLICE_X3Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 11.294 r DP/v1d_carry/O[3] net (fo=2, routed) 0.582 11.876 DP/read[3] SLICE_X4Y19 r DP/rw_reg_value[3]_i_1/I2 SLICE_X4Y19 LUT3 (Prop_lut3_I2_O) 0.306 12.182 r DP/rw_reg_value[3]_i_1/O net (fo=1, routed) 0.000 12.182 DP/rw_out[3] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 14.847 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[3]/C clock pessimism 0.297 15.144 clock uncertainty -0.035 15.109 SLICE_X4Y19 FDCE (Setup_fdce_C_D) 0.031 15.140 DP/rw_reg_value_reg[3] ------------------------------------------------------------------- required time 15.140 arrival time -12.182 ------------------------------------------------------------------- slack 2.957 Slack (MET) : 3.110ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 6.884ns (logic 3.990ns (57.962%) route 2.894ns (42.038%)) Logic Levels: 10 (CARRY4=5 LUT2=2 LUT3=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns = ( 14.847 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 9.870 r DP/w10_carry/O[0] net (fo=1, routed) 0.474 10.344 DP/w10[0] SLICE_X3Y18 r DP/v1d_carry_i_4/I0 SLICE_X3Y18 LUT3 (Prop_lut3_I0_O) 0.299 10.643 r DP/v1d_carry_i_4/O net (fo=1, routed) 0.000 10.643 DP/v1d_carry_i_4_n_0 SLICE_X3Y18 r DP/v1d_carry/S[0] SLICE_X3Y18 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 11.067 r DP/v1d_carry/O[1] net (fo=2, routed) 0.659 11.725 DP/read[1] SLICE_X4Y19 r DP/rw_reg_value[1]_i_1/I2 SLICE_X4Y19 LUT3 (Prop_lut3_I2_O) 0.303 12.028 r DP/rw_reg_value[1]_i_1/O net (fo=1, routed) 0.000 12.028 DP/rw_out[1] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 14.847 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[1]/C clock pessimism 0.297 15.144 clock uncertainty -0.035 15.109 SLICE_X4Y19 FDCE (Setup_fdce_C_D) 0.029 15.138 DP/rw_reg_value_reg[1] ------------------------------------------------------------------- required time 15.138 arrival time -12.028 ------------------------------------------------------------------- slack 3.110 Slack (MET) : 3.161ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 6.834ns (logic 4.326ns (63.298%) route 2.508ns (36.702%)) Logic Levels: 10 (CARRY4=5 LUT2=2 LUT3=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns = ( 14.847 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 10.047 r DP/w10_carry/O[1] net (fo=1, routed) 0.304 10.351 DP/w10[1] SLICE_X3Y18 r DP/v1d_carry_i_3/I0 SLICE_X3Y18 LUT3 (Prop_lut3_I0_O) 0.303 10.654 r DP/v1d_carry_i_3/O net (fo=1, routed) 0.000 10.654 DP/v1d_carry_i_3_n_0 SLICE_X3Y18 r DP/v1d_carry/S[1] SLICE_X3Y18 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 11.234 r DP/v1d_carry/O[2] net (fo=2, routed) 0.443 11.677 DP/read[2] SLICE_X4Y19 r DP/rw_reg_value[2]_i_1/I2 SLICE_X4Y19 LUT3 (Prop_lut3_I2_O) 0.302 11.979 r DP/rw_reg_value[2]_i_1/O net (fo=1, routed) 0.000 11.979 DP/rw_out[2] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 14.847 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[2]/C clock pessimism 0.297 15.144 clock uncertainty -0.035 15.109 SLICE_X4Y19 FDCE (Setup_fdce_C_D) 0.031 15.140 DP/rw_reg_value_reg[2] ------------------------------------------------------------------- required time 15.140 arrival time -11.979 ------------------------------------------------------------------- slack 3.161 Slack (MET) : 3.253ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/c_reg_value_reg[7]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 6.728ns (logic 4.376ns (65.042%) route 2.352ns (34.958%)) Logic Levels: 10 (CARRY4=6 LUT2=2 LUT3=2) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.260ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.155 r DP/w10_carry/CO[3] net (fo=1, routed) 0.000 10.155 DP/w10_carry_n_0 SLICE_X5Y19 r DP/w10_carry__0/CI SLICE_X5Y19 CARRY4 (Prop_carry4_CI_O[0]) 0.222 10.377 r DP/w10_carry__0/O[0] net (fo=1, routed) 0.591 10.967 DP/w10[4] SLICE_X3Y19 r DP/v1d_carry__0_i_4/I0 SLICE_X3Y19 LUT3 (Prop_lut3_I0_O) 0.299 11.266 r DP/v1d_carry__0_i_4/O net (fo=1, routed) 0.000 11.266 DP/v1d_carry__0_i_4_n_0 SLICE_X3Y19 r DP/v1d_carry__0/S[0] SLICE_X3Y19 CARRY4 (Prop_carry4_S[0]_O[3]) 0.606 11.872 r DP/v1d_carry__0/O[3] net (fo=2, routed) 0.000 11.872 DP/read[7] SLICE_X3Y19 FDCE r DP/c_reg_value_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.508 14.849 DP/CLK SLICE_X3Y19 FDCE r DP/c_reg_value_reg[7]/C clock pessimism 0.260 15.109 clock uncertainty -0.035 15.074 SLICE_X3Y19 FDCE (Setup_fdce_C_D) 0.051 15.125 DP/c_reg_value_reg[7] ------------------------------------------------------------------- required time 15.125 arrival time -11.872 ------------------------------------------------------------------- slack 3.253 Slack (MET) : 3.312ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/c_reg_value_reg[6]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 6.669ns (logic 4.317ns (64.733%) route 2.352ns (35.267%)) Logic Levels: 10 (CARRY4=6 LUT2=2 LUT3=2) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.260ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.155 r DP/w10_carry/CO[3] net (fo=1, routed) 0.000 10.155 DP/w10_carry_n_0 SLICE_X5Y19 r DP/w10_carry__0/CI SLICE_X5Y19 CARRY4 (Prop_carry4_CI_O[0]) 0.222 10.377 r DP/w10_carry__0/O[0] net (fo=1, routed) 0.591 10.967 DP/w10[4] SLICE_X3Y19 r DP/v1d_carry__0_i_4/I0 SLICE_X3Y19 LUT3 (Prop_lut3_I0_O) 0.299 11.266 r DP/v1d_carry__0_i_4/O net (fo=1, routed) 0.000 11.266 DP/v1d_carry__0_i_4_n_0 SLICE_X3Y19 r DP/v1d_carry__0/S[0] SLICE_X3Y19 CARRY4 (Prop_carry4_S[0]_O[2]) 0.547 11.813 r DP/v1d_carry__0/O[2] net (fo=2, routed) 0.000 11.813 DP/read[6] SLICE_X3Y19 FDCE r DP/c_reg_value_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.508 14.849 DP/CLK SLICE_X3Y19 FDCE r DP/c_reg_value_reg[6]/C clock pessimism 0.260 15.109 clock uncertainty -0.035 15.074 SLICE_X3Y19 FDCE (Setup_fdce_C_D) 0.051 15.125 DP/c_reg_value_reg[6] ------------------------------------------------------------------- required time 15.125 arrival time -11.813 ------------------------------------------------------------------- slack 3.312 Slack (MET) : 3.335ns (required time - arrival time) Source: DP/rw_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/rw_reg_value_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 6.625ns (logic 3.809ns (57.493%) route 2.816ns (42.507%)) Logic Levels: 10 (CARRY4=5 LUT2=2 LUT3=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 ) Source Clock Delay (SCD): 5.144ns Clock Pessimism Removal (CPR): 0.260ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.623 5.144 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.419 5.563 r DP/rw_reg_value_reg[6]/Q net (fo=5, routed) 0.550 6.113 DP/w000[1] SLICE_X2Y18 r DP/w00_carry_i_2/I1 SLICE_X2Y18 LUT2 (Prop_lut2_I1_O) 0.296 6.409 r DP/w00_carry_i_2/O net (fo=1, routed) 0.000 6.409 DP/w00_carry_i_2_n_0 SLICE_X2Y18 r DP/w00_carry/S[1] SLICE_X2Y18 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 7.052 r DP/w00_carry/O[3] net (fo=1, routed) 0.602 7.654 DP/w00[3] SLICE_X1Y18 r DP/v0d_carry_i_1/I0 SLICE_X1Y18 LUT3 (Prop_lut3_I0_O) 0.307 7.961 r DP/v0d_carry_i_1/O net (fo=1, routed) 0.000 7.961 DP/v0d_carry_i_1_n_0 SLICE_X1Y18 r DP/v0d_carry/S[3] SLICE_X1Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 8.362 r DP/v0d_carry/CO[3] net (fo=1, routed) 0.000 8.362 DP/v0d_carry_n_0 SLICE_X1Y19 r DP/v0d_carry__0/CI SLICE_X1Y19 CARRY4 (Prop_carry4_CI_O[1]) 0.348 8.710 r DP/v0d_carry__0/O[1] net (fo=5, routed) 0.609 9.320 DP/read[13] SLICE_X5Y18 r DP/w10_carry_i_3/I1 SLICE_X5Y18 LUT2 (Prop_lut2_I1_O) 0.303 9.623 r DP/w10_carry_i_3/O net (fo=1, routed) 0.000 9.623 DP/w10_carry_i_3_n_0 SLICE_X5Y18 r DP/w10_carry/S[0] SLICE_X5Y18 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 9.870 r DP/w10_carry/O[0] net (fo=1, routed) 0.474 10.344 DP/w10[0] SLICE_X3Y18 r DP/v1d_carry_i_4/I0 SLICE_X3Y18 LUT3 (Prop_lut3_I0_O) 0.299 10.643 r DP/v1d_carry_i_4/O net (fo=1, routed) 0.000 10.643 DP/v1d_carry_i_4_n_0 SLICE_X3Y18 r DP/v1d_carry/S[0] SLICE_X3Y18 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 10.890 r DP/v1d_carry/O[0] net (fo=2, routed) 0.581 11.470 DP/read[0] SLICE_X0Y18 r DP/rw_reg_value[0]_i_1/I2 SLICE_X0Y18 LUT3 (Prop_lut3_I2_O) 0.299 11.769 r DP/rw_reg_value[0]_i_1/O net (fo=1, routed) 0.000 11.769 DP/rw_out[0] SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.509 14.850 DP/CLK SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[0]/C clock pessimism 0.260 15.110 clock uncertainty -0.035 15.075 SLICE_X0Y18 FDCE (Setup_fdce_C_D) 0.029 15.104 DP/rw_reg_value_reg[0] ------------------------------------------------------------------- required time 15.104 arrival time -11.769 ------------------------------------------------------------------- slack 3.335 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.162ns (arrival time - required time) Source: DP/counter_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: SM/FSM_sequential_curstate_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.295ns (logic 0.186ns (63.028%) route 0.109ns (36.972%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.472ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.589 1.472 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y17 FDCE (Prop_fdce_C_Q) 0.141 1.613 f DP/counter_reg[0]/Q net (fo=6, routed) 0.109 1.722 DP/counter_reg__0[0] SLICE_X2Y17 f DP/FSM_sequential_curstate[0]_i_1/I1 SLICE_X2Y17 LUT6 (Prop_lut6_I1_O) 0.045 1.767 r DP/FSM_sequential_curstate[0]_i_1/O net (fo=1, routed) 0.000 1.767 SM/D[0] SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.858 1.985 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[0]/C clock pessimism -0.500 1.485 SLICE_X2Y17 FDCE (Hold_fdce_C_D) 0.120 1.605 SM/FSM_sequential_curstate_reg[0] ------------------------------------------------------------------- required time -1.605 arrival time 1.767 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.250ns (arrival time - required time) Source: DP/s_reg_value_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/s_reg_value_reg[5]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.354ns (logic 0.186ns (52.470%) route 0.168ns (47.530%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.979ns Source Clock Delay (SCD): 1.467ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.584 1.467 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y20 FDCE (Prop_fdce_C_Q) 0.141 1.608 r DP/s_reg_value_reg[4]/Q net (fo=8, routed) 0.168 1.777 DP/s_reg_value_reg__0[4] SLICE_X4Y21 r DP/s_reg_value[5]_i_1/I0 SLICE_X4Y21 LUT6 (Prop_lut6_I0_O) 0.045 1.822 r DP/s_reg_value[5]_i_1/O net (fo=1, routed) 0.000 1.822 DP/s_out[5] SLICE_X4Y21 FDCE r DP/s_reg_value_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.852 1.979 DP/CLK SLICE_X4Y21 FDCE r DP/s_reg_value_reg[5]/C clock pessimism -0.499 1.480 SLICE_X4Y21 FDCE (Hold_fdce_C_D) 0.091 1.571 DP/s_reg_value_reg[5] ------------------------------------------------------------------- required time -1.571 arrival time 1.822 ------------------------------------------------------------------- slack 0.250 Slack (MET) : 0.257ns (arrival time - required time) Source: DP/counter_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.364ns (logic 0.184ns (50.535%) route 0.180ns (49.465%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.472ns Clock Pessimism Removal (CPR): 0.513ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.589 1.472 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y17 FDCE (Prop_fdce_C_Q) 0.141 1.613 r DP/counter_reg[0]/Q net (fo=6, routed) 0.180 1.793 DP/counter_reg__0[0] SLICE_X3Y17 r DP/counter[3]_i_1/I1 SLICE_X3Y17 LUT4 (Prop_lut4_I1_O) 0.043 1.836 r DP/counter[3]_i_1/O net (fo=1, routed) 0.000 1.836 DP/plusOp[3] SLICE_X3Y17 FDCE r DP/counter_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.858 1.985 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[3]/C clock pessimism -0.513 1.472 SLICE_X3Y17 FDCE (Hold_fdce_C_D) 0.107 1.579 DP/counter_reg[3] ------------------------------------------------------------------- required time -1.579 arrival time 1.836 ------------------------------------------------------------------- slack 0.257 Slack (MET) : 0.260ns (arrival time - required time) Source: DP/s_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/s_reg_value_reg[7]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.365ns (logic 0.186ns (50.990%) route 0.179ns (49.010%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.979ns Source Clock Delay (SCD): 1.467ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.584 1.467 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y20 FDCE (Prop_fdce_C_Q) 0.141 1.608 r DP/s_reg_value_reg[6]/Q net (fo=9, routed) 0.179 1.787 DP/s_reg_value_reg__0[6] SLICE_X4Y21 r DP/s_reg_value[7]_i_1/I3 SLICE_X4Y21 LUT5 (Prop_lut5_I3_O) 0.045 1.832 r DP/s_reg_value[7]_i_1/O net (fo=1, routed) 0.000 1.832 DP/s_out[7] SLICE_X4Y21 FDCE r DP/s_reg_value_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.852 1.979 DP/CLK SLICE_X4Y21 FDCE r DP/s_reg_value_reg[7]/C clock pessimism -0.499 1.480 SLICE_X4Y21 FDCE (Hold_fdce_C_D) 0.092 1.572 DP/s_reg_value_reg[7] ------------------------------------------------------------------- required time -1.572 arrival time 1.832 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.268ns (arrival time - required time) Source: DP/rw_reg_value_reg[14]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/c_reg_value_reg[15]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.383ns (logic 0.309ns (80.773%) route 0.074ns (19.226%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.983ns Source Clock Delay (SCD): 1.470ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.587 1.470 DP/CLK SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y19 FDCE (Prop_fdce_C_Q) 0.128 1.598 r DP/rw_reg_value_reg[14]/Q net (fo=2, routed) 0.074 1.672 DP/v0[6] SLICE_X1Y19 r DP/v0d_carry__0/DI[2] SLICE_X1Y19 CARRY4 (Prop_carry4_DI[2]_O[3]) 0.181 1.853 r DP/v0d_carry__0/O[3] net (fo=4, routed) 0.000 1.853 DP/read[15] SLICE_X1Y19 FDCE r DP/c_reg_value_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.856 1.983 DP/CLK SLICE_X1Y19 FDCE r DP/c_reg_value_reg[15]/C clock pessimism -0.500 1.483 SLICE_X1Y19 FDCE (Hold_fdce_C_D) 0.102 1.585 DP/c_reg_value_reg[15] ------------------------------------------------------------------- required time -1.585 arrival time 1.853 ------------------------------------------------------------------- slack 0.268 Slack (MET) : 0.274ns (arrival time - required time) Source: DP/counter_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.366ns (logic 0.186ns (50.805%) route 0.180ns (49.195%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.472ns Clock Pessimism Removal (CPR): 0.513ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.589 1.472 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y17 FDCE (Prop_fdce_C_Q) 0.141 1.613 r DP/counter_reg[0]/Q net (fo=6, routed) 0.180 1.793 DP/counter_reg__0[0] SLICE_X3Y17 r DP/counter[2]_i_1/I0 SLICE_X3Y17 LUT3 (Prop_lut3_I0_O) 0.045 1.838 r DP/counter[2]_i_1/O net (fo=1, routed) 0.000 1.838 DP/plusOp[2] SLICE_X3Y17 FDCE r DP/counter_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.858 1.985 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[2]/C clock pessimism -0.513 1.472 SLICE_X3Y17 FDCE (Hold_fdce_C_D) 0.092 1.564 DP/counter_reg[2] ------------------------------------------------------------------- required time -1.564 arrival time 1.838 ------------------------------------------------------------------- slack 0.274 Slack (MET) : 0.275ns (arrival time - required time) Source: DP/rw_reg_value_reg[8]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/c_reg_value_reg[9]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.390ns (logic 0.265ns (67.967%) route 0.125ns (32.033%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 1.471ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.588 1.471 DP/CLK SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y18 FDCE (Prop_fdce_C_Q) 0.141 1.612 r DP/rw_reg_value_reg[8]/Q net (fo=2, routed) 0.125 1.737 DP/v0[0] SLICE_X1Y18 r DP/v0d_carry/DI[0] SLICE_X1Y18 CARRY4 (Prop_carry4_DI[0]_O[1]) 0.124 1.861 r DP/v0d_carry/O[1] net (fo=5, routed) 0.000 1.861 DP/read[9] SLICE_X1Y18 FDCE r DP/c_reg_value_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.857 1.984 DP/CLK SLICE_X1Y18 FDCE r DP/c_reg_value_reg[9]/C clock pessimism -0.500 1.484 SLICE_X1Y18 FDCE (Hold_fdce_C_D) 0.102 1.586 DP/c_reg_value_reg[9] ------------------------------------------------------------------- required time -1.586 arrival time 1.861 ------------------------------------------------------------------- slack 0.275 Slack (MET) : 0.290ns (arrival time - required time) Source: DP/rw_reg_value_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/c_reg_value_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.430ns (logic 0.251ns (58.356%) route 0.179ns (41.644%)) Logic Levels: 2 (CARRY4=1 LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 1.468ns Clock Pessimism Removal (CPR): 0.478ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.585 1.468 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y19 FDCE (Prop_fdce_C_Q) 0.141 1.609 r DP/rw_reg_value_reg[1]/Q net (fo=5, routed) 0.179 1.788 DP/w000[5] SLICE_X3Y18 r DP/v1d_carry_i_3/I2 SLICE_X3Y18 LUT3 (Prop_lut3_I2_O) 0.045 1.833 r DP/v1d_carry_i_3/O net (fo=1, routed) 0.000 1.833 DP/v1d_carry_i_3_n_0 SLICE_X3Y18 r DP/v1d_carry/S[1] SLICE_X3Y18 CARRY4 (Prop_carry4_S[1]_O[1]) 0.065 1.898 r DP/v1d_carry/O[1] net (fo=2, routed) 0.000 1.898 DP/read[1] SLICE_X3Y18 FDCE r DP/c_reg_value_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.857 1.984 DP/CLK SLICE_X3Y18 FDCE r DP/c_reg_value_reg[1]/C clock pessimism -0.478 1.506 SLICE_X3Y18 FDCE (Hold_fdce_C_D) 0.102 1.608 DP/c_reg_value_reg[1] ------------------------------------------------------------------- required time -1.608 arrival time 1.898 ------------------------------------------------------------------- slack 0.290 Slack (MET) : 0.307ns (arrival time - required time) Source: DP/s_reg_value_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/s_reg_value_reg[4]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.399ns (logic 0.226ns (56.664%) route 0.173ns (43.336%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.980ns Source Clock Delay (SCD): 1.467ns Clock Pessimism Removal (CPR): 0.513ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.584 1.467 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y20 FDCE (Prop_fdce_C_Q) 0.128 1.595 r DP/s_reg_value_reg[3]/Q net (fo=9, routed) 0.173 1.768 DP/s_reg_value_reg__0[3] SLICE_X4Y20 r DP/s_reg_value[4]_i_1/I0 SLICE_X4Y20 LUT6 (Prop_lut6_I0_O) 0.098 1.866 r DP/s_reg_value[4]_i_1/O net (fo=1, routed) 0.000 1.866 DP/s_out[4] SLICE_X4Y20 FDCE r DP/s_reg_value_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.853 1.980 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[4]/C clock pessimism -0.513 1.467 SLICE_X4Y20 FDCE (Hold_fdce_C_D) 0.092 1.559 DP/s_reg_value_reg[4] ------------------------------------------------------------------- required time -1.559 arrival time 1.866 ------------------------------------------------------------------- slack 0.307 Slack (MET) : 0.308ns (arrival time - required time) Source: DP/rw_reg_value_reg[8]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/c_reg_value_reg[10]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.423ns (logic 0.298ns (70.467%) route 0.125ns (29.533%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 1.471ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.588 1.471 DP/CLK SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y18 FDCE (Prop_fdce_C_Q) 0.141 1.612 r DP/rw_reg_value_reg[8]/Q net (fo=2, routed) 0.125 1.737 DP/v0[0] SLICE_X1Y18 r DP/v0d_carry/DI[0] SLICE_X1Y18 CARRY4 (Prop_carry4_DI[0]_O[2]) 0.157 1.894 r DP/v0d_carry/O[2] net (fo=5, routed) 0.000 1.894 DP/read[10] SLICE_X1Y18 FDCE r DP/c_reg_value_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.857 1.984 DP/CLK SLICE_X1Y18 FDCE r DP/c_reg_value_reg[10]/C clock pessimism -0.500 1.484 SLICE_X1Y18 FDCE (Hold_fdce_C_D) 0.102 1.586 DP/c_reg_value_reg[10] ------------------------------------------------------------------- required time -1.586 arrival time 1.894 ------------------------------------------------------------------- slack 0.308 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk_pin Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X3Y18 DP/c_reg_value_reg[0]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X1Y18 DP/c_reg_value_reg[10]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X1Y18 DP/c_reg_value_reg[11]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X1Y19 DP/c_reg_value_reg[12]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X1Y19 DP/c_reg_value_reg[13]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X1Y19 DP/c_reg_value_reg[14]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X1Y19 DP/c_reg_value_reg[15]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X3Y18 DP/c_reg_value_reg[1]/C Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X3Y18 DP/c_reg_value_reg[2]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y18 DP/c_reg_value_reg[0]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y18 DP/c_reg_value_reg[10]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y18 DP/c_reg_value_reg[11]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y19 DP/c_reg_value_reg[12]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y19 DP/c_reg_value_reg[13]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y19 DP/c_reg_value_reg[14]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y19 DP/c_reg_value_reg[15]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y18 DP/c_reg_value_reg[1]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y18 DP/c_reg_value_reg[2]/C Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y18 DP/c_reg_value_reg[3]/C High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y17 DP/counter_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y17 DP/counter_reg[1]/C High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y17 DP/counter_reg[2]/C High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y17 DP/counter_reg[3]/C High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X2Y17 SM/FSM_sequential_curstate_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X2Y17 SM/FSM_sequential_curstate_reg[1]/C High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X3Y18 DP/c_reg_value_reg[0]/C High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y18 DP/c_reg_value_reg[10]/C High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y18 DP/c_reg_value_reg[11]/C High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X1Y19 DP/c_reg_value_reg[12]/C --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk_pin To Clock: sys_clk_pin Setup : 0 Failing Endpoints, Worst Slack 7.532ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.736ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.532ns (required time - arrival time) Source: SM/FSM_sequential_curstate_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[0]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 1.782ns (logic 0.766ns (42.990%) route 1.016ns (57.010%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) Source Clock Delay (SCD): 5.150ns Clock Pessimism Removal (CPR): 0.276ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.629 5.150 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.478 5.628 r SM/FSM_sequential_curstate_reg[1]/Q net (fo=5, routed) 0.482 6.111 SM/Q[1] SLICE_X2Y17 r SM/counter[3]_i_2/I2 SLICE_X2Y17 LUT4 (Prop_lut4_I2_O) 0.288 6.399 f SM/counter[3]_i_2/O net (fo=4, routed) 0.533 6.932 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.511 14.852 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[0]/C clock pessimism 0.276 15.128 clock uncertainty -0.035 15.093 SLICE_X3Y17 FDCE (Recov_fdce_C_CLR) -0.629 14.464 DP/counter_reg[0] ------------------------------------------------------------------- required time 14.464 arrival time -6.932 ------------------------------------------------------------------- slack 7.532 Slack (MET) : 7.532ns (required time - arrival time) Source: SM/FSM_sequential_curstate_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[1]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 1.782ns (logic 0.766ns (42.990%) route 1.016ns (57.010%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) Source Clock Delay (SCD): 5.150ns Clock Pessimism Removal (CPR): 0.276ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.629 5.150 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.478 5.628 r SM/FSM_sequential_curstate_reg[1]/Q net (fo=5, routed) 0.482 6.111 SM/Q[1] SLICE_X2Y17 r SM/counter[3]_i_2/I2 SLICE_X2Y17 LUT4 (Prop_lut4_I2_O) 0.288 6.399 f SM/counter[3]_i_2/O net (fo=4, routed) 0.533 6.932 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.511 14.852 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[1]/C clock pessimism 0.276 15.128 clock uncertainty -0.035 15.093 SLICE_X3Y17 FDCE (Recov_fdce_C_CLR) -0.629 14.464 DP/counter_reg[1] ------------------------------------------------------------------- required time 14.464 arrival time -6.932 ------------------------------------------------------------------- slack 7.532 Slack (MET) : 7.532ns (required time - arrival time) Source: SM/FSM_sequential_curstate_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[2]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 1.782ns (logic 0.766ns (42.990%) route 1.016ns (57.010%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) Source Clock Delay (SCD): 5.150ns Clock Pessimism Removal (CPR): 0.276ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.629 5.150 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.478 5.628 r SM/FSM_sequential_curstate_reg[1]/Q net (fo=5, routed) 0.482 6.111 SM/Q[1] SLICE_X2Y17 r SM/counter[3]_i_2/I2 SLICE_X2Y17 LUT4 (Prop_lut4_I2_O) 0.288 6.399 f SM/counter[3]_i_2/O net (fo=4, routed) 0.533 6.932 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.511 14.852 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[2]/C clock pessimism 0.276 15.128 clock uncertainty -0.035 15.093 SLICE_X3Y17 FDCE (Recov_fdce_C_CLR) -0.629 14.464 DP/counter_reg[2] ------------------------------------------------------------------- required time 14.464 arrival time -6.932 ------------------------------------------------------------------- slack 7.532 Slack (MET) : 7.532ns (required time - arrival time) Source: SM/FSM_sequential_curstate_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[3]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 1.782ns (logic 0.766ns (42.990%) route 1.016ns (57.010%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) Source Clock Delay (SCD): 5.150ns Clock Pessimism Removal (CPR): 0.276ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.629 5.150 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.478 5.628 r SM/FSM_sequential_curstate_reg[1]/Q net (fo=5, routed) 0.482 6.111 SM/Q[1] SLICE_X2Y17 r SM/counter[3]_i_2/I2 SLICE_X2Y17 LUT4 (Prop_lut4_I2_O) 0.288 6.399 f SM/counter[3]_i_2/O net (fo=4, routed) 0.533 6.932 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 10.000 10.000 r W5 0.000 10.000 r clk (IN) net (fo=0) 0.000 10.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 13.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.511 14.852 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[3]/C clock pessimism 0.276 15.128 clock uncertainty -0.035 15.093 SLICE_X3Y17 FDCE (Recov_fdce_C_CLR) -0.629 14.464 DP/counter_reg[3] ------------------------------------------------------------------- required time 14.464 arrival time -6.932 ------------------------------------------------------------------- slack 7.532 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.736ns (arrival time - required time) Source: SM/FSM_sequential_curstate_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[0]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.584ns (logic 0.207ns (35.453%) route 0.377ns (64.547%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.472ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.589 1.472 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.164 1.636 r SM/FSM_sequential_curstate_reg[0]/Q net (fo=5, routed) 0.197 1.834 SM/Q[0] SLICE_X2Y17 r SM/counter[3]_i_2/I1 SLICE_X2Y17 LUT4 (Prop_lut4_I1_O) 0.043 1.877 f SM/counter[3]_i_2/O net (fo=4, routed) 0.179 2.056 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.858 1.985 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[0]/C clock pessimism -0.500 1.485 SLICE_X3Y17 FDCE (Remov_fdce_C_CLR) -0.165 1.320 DP/counter_reg[0] ------------------------------------------------------------------- required time -1.320 arrival time 2.056 ------------------------------------------------------------------- slack 0.736 Slack (MET) : 0.736ns (arrival time - required time) Source: SM/FSM_sequential_curstate_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[1]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.584ns (logic 0.207ns (35.453%) route 0.377ns (64.547%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.472ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.589 1.472 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.164 1.636 r SM/FSM_sequential_curstate_reg[0]/Q net (fo=5, routed) 0.197 1.834 SM/Q[0] SLICE_X2Y17 r SM/counter[3]_i_2/I1 SLICE_X2Y17 LUT4 (Prop_lut4_I1_O) 0.043 1.877 f SM/counter[3]_i_2/O net (fo=4, routed) 0.179 2.056 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.858 1.985 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[1]/C clock pessimism -0.500 1.485 SLICE_X3Y17 FDCE (Remov_fdce_C_CLR) -0.165 1.320 DP/counter_reg[1] ------------------------------------------------------------------- required time -1.320 arrival time 2.056 ------------------------------------------------------------------- slack 0.736 Slack (MET) : 0.736ns (arrival time - required time) Source: SM/FSM_sequential_curstate_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[2]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.584ns (logic 0.207ns (35.453%) route 0.377ns (64.547%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.472ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.589 1.472 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.164 1.636 r SM/FSM_sequential_curstate_reg[0]/Q net (fo=5, routed) 0.197 1.834 SM/Q[0] SLICE_X2Y17 r SM/counter[3]_i_2/I1 SLICE_X2Y17 LUT4 (Prop_lut4_I1_O) 0.043 1.877 f SM/counter[3]_i_2/O net (fo=4, routed) 0.179 2.056 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.858 1.985 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[2]/C clock pessimism -0.500 1.485 SLICE_X3Y17 FDCE (Remov_fdce_C_CLR) -0.165 1.320 DP/counter_reg[2] ------------------------------------------------------------------- required time -1.320 arrival time 2.056 ------------------------------------------------------------------- slack 0.736 Slack (MET) : 0.736ns (arrival time - required time) Source: SM/FSM_sequential_curstate_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: DP/counter_reg[3]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.584ns (logic 0.207ns (35.453%) route 0.377ns (64.547%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.472ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.589 1.472 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.164 1.636 r SM/FSM_sequential_curstate_reg[0]/Q net (fo=5, routed) 0.197 1.834 SM/Q[0] SLICE_X2Y17 r SM/counter[3]_i_2/I1 SLICE_X2Y17 LUT4 (Prop_lut4_I1_O) 0.043 1.877 f SM/counter[3]_i_2/O net (fo=4, routed) 0.179 2.056 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.858 1.985 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[3]/C clock pessimism -0.500 1.485 SLICE_X3Y17 FDCE (Remov_fdce_C_CLR) -0.165 1.320 DP/counter_reg[3] ------------------------------------------------------------------- required time -1.320 arrival time 2.056 ------------------------------------------------------------------- slack 0.736 -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk_pin To Clock: Max Delay 17 Endpoints Min Delay 17 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: SM/FSM_sequential_curstate_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: done (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.873ns (logic 3.241ns (55.185%) route 2.632ns (44.815%)) Logic Levels: 2 (LUT2=1 OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.629 5.150 SM/CLK SLICE_X2Y17 FDCE r SM/FSM_sequential_curstate_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y17 FDCE (Prop_fdce_C_Q) 0.518 5.668 f SM/FSM_sequential_curstate_reg[0]/Q net (fo=5, routed) 0.829 6.498 SM/Q[0] SLICE_X2Y17 f SM/done_OBUF_inst_i_1/I1 SLICE_X2Y17 LUT2 (Prop_lut2_I1_O) 0.124 6.622 r SM/done_OBUF_inst_i_1/O net (fo=1, routed) 1.802 8.424 done_OBUF T17 r done_OBUF_inst/I T17 OBUF (Prop_obuf_I_O) 2.599 11.023 r done_OBUF_inst/O net (fo=0) 0.000 11.023 done T17 r done (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.322ns (logic 3.055ns (57.409%) route 2.267ns (42.591%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.627 5.148 DP/CLK SLICE_X3Y18 FDCE r DP/c_reg_value_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y18 FDCE (Prop_fdce_C_Q) 0.456 5.604 r DP/c_reg_value_reg[0]/Q net (fo=1, routed) 2.267 7.871 c_OBUF[0] U14 r c_OBUF[0]_inst/I U14 OBUF (Prop_obuf_I_O) 2.599 10.470 r c_OBUF[0]_inst/O net (fo=0) 0.000 10.470 c[0] U14 r c[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.321ns (logic 3.054ns (57.389%) route 2.267ns (42.612%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.627 5.148 DP/CLK SLICE_X3Y18 FDCE r DP/c_reg_value_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y18 FDCE (Prop_fdce_C_Q) 0.456 5.604 r DP/c_reg_value_reg[3]/Q net (fo=1, routed) 2.267 7.872 c_OBUF[3] U16 r c_OBUF[3]_inst/I U16 OBUF (Prop_obuf_I_O) 2.598 10.469 r c_OBUF[3]_inst/O net (fo=0) 0.000 10.469 c[3] U16 r c[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.275ns (logic 3.063ns (58.060%) route 2.212ns (41.940%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.626 5.147 DP/CLK SLICE_X3Y19 FDCE r DP/c_reg_value_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y19 FDCE (Prop_fdce_C_Q) 0.456 5.603 r DP/c_reg_value_reg[6]/Q net (fo=1, routed) 2.212 7.816 c_OBUF[6] W13 r c_OBUF[6]_inst/I W13 OBUF (Prop_obuf_I_O) 2.607 10.422 r c_OBUF[6]_inst/O net (fo=0) 0.000 10.422 c[6] W13 r c[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.259ns (logic 3.054ns (58.063%) route 2.206ns (41.937%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.626 5.147 DP/CLK SLICE_X3Y19 FDCE r DP/c_reg_value_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y19 FDCE (Prop_fdce_C_Q) 0.456 5.603 r DP/c_reg_value_reg[5]/Q net (fo=1, routed) 2.206 7.809 c_OBUF[5] W14 r c_OBUF[5]_inst/I W14 OBUF (Prop_obuf_I_O) 2.598 10.406 r c_OBUF[5]_inst/O net (fo=0) 0.000 10.406 c[5] W14 r c[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.193ns (logic 3.063ns (58.990%) route 2.130ns (41.010%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.626 5.147 DP/CLK SLICE_X3Y19 FDCE r DP/c_reg_value_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y19 FDCE (Prop_fdce_C_Q) 0.456 5.603 r DP/c_reg_value_reg[4]/Q net (fo=1, routed) 2.130 7.733 c_OBUF[4] U15 r c_OBUF[4]_inst/I U15 OBUF (Prop_obuf_I_O) 2.607 10.341 r c_OBUF[4]_inst/O net (fo=0) 0.000 10.341 c[4] U15 r c[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.175ns (logic 3.050ns (58.929%) route 2.125ns (41.071%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.627 5.148 DP/CLK SLICE_X3Y18 FDCE r DP/c_reg_value_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y18 FDCE (Prop_fdce_C_Q) 0.456 5.604 r DP/c_reg_value_reg[1]/Q net (fo=1, routed) 2.125 7.730 c_OBUF[1] V14 r c_OBUF[1]_inst/I V14 OBUF (Prop_obuf_I_O) 2.594 10.323 r c_OBUF[1]_inst/O net (fo=0) 0.000 10.323 c[1] V14 r c[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.172ns (logic 3.053ns (59.035%) route 2.119ns (40.965%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.627 5.148 DP/CLK SLICE_X3Y18 FDCE r DP/c_reg_value_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y18 FDCE (Prop_fdce_C_Q) 0.456 5.604 r DP/c_reg_value_reg[2]/Q net (fo=1, routed) 2.119 7.723 c_OBUF[2] V13 r c_OBUF[2]_inst/I V13 OBUF (Prop_obuf_I_O) 2.597 10.320 r c_OBUF[2]_inst/O net (fo=0) 0.000 10.320 c[2] V13 r c[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.160ns (logic 3.055ns (59.191%) route 2.106ns (40.809%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.626 5.147 DP/CLK SLICE_X3Y19 FDCE r DP/c_reg_value_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y19 FDCE (Prop_fdce_C_Q) 0.456 5.603 r DP/c_reg_value_reg[7]/Q net (fo=1, routed) 2.106 7.709 c_OBUF[7] W15 r c_OBUF[7]_inst/I W15 OBUF (Prop_obuf_I_O) 2.599 10.308 r c_OBUF[7]_inst/O net (fo=0) 0.000 10.308 c[7] W15 r c[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[8]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[8] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 5.141ns (logic 3.070ns (59.710%) route 2.071ns (40.290%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O net (fo=1, routed) 1.967 3.425 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.627 5.148 DP/CLK SLICE_X1Y18 FDCE r DP/c_reg_value_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y18 FDCE (Prop_fdce_C_Q) 0.456 5.604 r DP/c_reg_value_reg[8]/Q net (fo=1, routed) 2.071 7.676 c_OBUF[8] V15 r c_OBUF[8]_inst/I V15 OBUF (Prop_obuf_I_O) 2.614 10.290 r c_OBUF[8]_inst/O net (fo=0) 0.000 10.290 c[8] V15 r c[8] (OUT) ------------------------------------------------------------------- ------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: DP/c_reg_value_reg[13]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[13] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.611ns (logic 1.247ns (77.415%) route 0.364ns (22.585%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.587 1.470 DP/CLK SLICE_X1Y19 FDCE r DP/c_reg_value_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y19 FDCE (Prop_fdce_C_Q) 0.141 1.611 r DP/c_reg_value_reg[13]/Q net (fo=1, routed) 0.364 1.975 c_OBUF[13] U18 r c_OBUF[13]_inst/I U18 OBUF (Prop_obuf_I_O) 1.106 3.081 r c_OBUF[13]_inst/O net (fo=0) 0.000 3.081 c[13] U18 r c[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[15]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[15] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.620ns (logic 1.260ns (77.743%) route 0.361ns (22.257%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.587 1.470 DP/CLK SLICE_X1Y19 FDCE r DP/c_reg_value_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y19 FDCE (Prop_fdce_C_Q) 0.141 1.611 r DP/c_reg_value_reg[15]/Q net (fo=1, routed) 0.361 1.972 c_OBUF[15] T18 r c_OBUF[15]_inst/I T18 OBUF (Prop_obuf_I_O) 1.119 3.090 r c_OBUF[15]_inst/O net (fo=0) 0.000 3.090 c[15] T18 r c[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[14]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[14] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.676ns (logic 1.258ns (75.087%) route 0.417ns (24.913%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.587 1.470 DP/CLK SLICE_X1Y19 FDCE r DP/c_reg_value_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y19 FDCE (Prop_fdce_C_Q) 0.141 1.611 r DP/c_reg_value_reg[14]/Q net (fo=1, routed) 0.417 2.029 c_OBUF[14] U17 r c_OBUF[14]_inst/I U17 OBUF (Prop_obuf_I_O) 1.117 3.146 r c_OBUF[14]_inst/O net (fo=0) 0.000 3.146 c[14] U17 r c[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[12]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[12] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.689ns (logic 1.267ns (75.013%) route 0.422ns (24.987%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.587 1.470 DP/CLK SLICE_X1Y19 FDCE r DP/c_reg_value_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y19 FDCE (Prop_fdce_C_Q) 0.141 1.611 r DP/c_reg_value_reg[12]/Q net (fo=1, routed) 0.422 2.033 c_OBUF[12] V16 r c_OBUF[12]_inst/I V16 OBUF (Prop_obuf_I_O) 1.126 3.159 r c_OBUF[12]_inst/O net (fo=0) 0.000 3.159 c[12] V16 r c[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[9]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[9] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.698ns (logic 1.254ns (73.877%) route 0.444ns (26.123%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.588 1.471 DP/CLK SLICE_X1Y18 FDCE r DP/c_reg_value_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y18 FDCE (Prop_fdce_C_Q) 0.141 1.612 r DP/c_reg_value_reg[9]/Q net (fo=1, routed) 0.444 2.056 c_OBUF[9] W17 r c_OBUF[9]_inst/I W17 OBUF (Prop_obuf_I_O) 1.113 3.169 r c_OBUF[9]_inst/O net (fo=0) 0.000 3.169 c[9] W17 r c[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[10]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[10] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.707ns (logic 1.270ns (74.366%) route 0.438ns (25.634%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.588 1.471 DP/CLK SLICE_X1Y18 FDCE r DP/c_reg_value_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y18 FDCE (Prop_fdce_C_Q) 0.141 1.612 r DP/c_reg_value_reg[10]/Q net (fo=1, routed) 0.438 2.050 c_OBUF[10] W16 r c_OBUF[10]_inst/I W16 OBUF (Prop_obuf_I_O) 1.129 3.178 r c_OBUF[10]_inst/O net (fo=0) 0.000 3.178 c[10] W16 r c[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[11]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[11] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.738ns (logic 1.259ns (72.423%) route 0.479ns (27.577%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.588 1.471 DP/CLK SLICE_X1Y18 FDCE r DP/c_reg_value_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y18 FDCE (Prop_fdce_C_Q) 0.141 1.612 r DP/c_reg_value_reg[11]/Q net (fo=1, routed) 0.479 2.091 c_OBUF[11] V17 r c_OBUF[11]_inst/I V17 OBUF (Prop_obuf_I_O) 1.118 3.209 r c_OBUF[11]_inst/O net (fo=0) 0.000 3.209 c[11] V17 r c[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[8]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[8] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.764ns (logic 1.272ns (72.090%) route 0.492ns (27.910%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.588 1.471 DP/CLK SLICE_X1Y18 FDCE r DP/c_reg_value_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y18 FDCE (Prop_fdce_C_Q) 0.141 1.612 r DP/c_reg_value_reg[8]/Q net (fo=1, routed) 0.492 2.105 c_OBUF[8] V15 r c_OBUF[8]_inst/I V15 OBUF (Prop_obuf_I_O) 1.131 3.235 r c_OBUF[8]_inst/O net (fo=0) 0.000 3.235 c[8] V15 r c[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.771ns (logic 1.252ns (70.674%) route 0.519ns (29.326%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.588 1.471 DP/CLK SLICE_X3Y18 FDCE r DP/c_reg_value_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y18 FDCE (Prop_fdce_C_Q) 0.141 1.612 r DP/c_reg_value_reg[1]/Q net (fo=1, routed) 0.519 2.132 c_OBUF[1] V14 r c_OBUF[1]_inst/I V14 OBUF (Prop_obuf_I_O) 1.111 3.242 r c_OBUF[1]_inst/O net (fo=0) 0.000 3.242 c[1] V14 r c[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: DP/c_reg_value_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: c[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 1.777ns (logic 1.257ns (70.735%) route 0.520ns (29.265%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O net (fo=1, routed) 0.631 0.858 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.587 1.470 DP/CLK SLICE_X3Y19 FDCE r DP/c_reg_value_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y19 FDCE (Prop_fdce_C_Q) 0.141 1.611 r DP/c_reg_value_reg[7]/Q net (fo=1, routed) 0.520 2.131 c_OBUF[7] W15 r c_OBUF[7]_inst/I W15 OBUF (Prop_obuf_I_O) 1.116 3.247 r c_OBUF[7]_inst/O net (fo=0) 0.000 3.247 c[7] W15 r c[7] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk_pin Max Delay 99 Endpoints Min Delay 99 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[5]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.160ns (logic 1.058ns (25.425%) route 3.102ns (74.575%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.846ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.846ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.809 4.160 DP/E[0] SLICE_X4Y21 FDCE r DP/s_reg_value_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.505 4.846 DP/CLK SLICE_X4Y21 FDCE r DP/s_reg_value_reg[5]/C Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[7]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.160ns (logic 1.058ns (25.425%) route 3.102ns (74.575%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.846ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.846ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.809 4.160 DP/E[0] SLICE_X4Y21 FDCE r DP/s_reg_value_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.505 4.846 DP/CLK SLICE_X4Y21 FDCE r DP/s_reg_value_reg[7]/C Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[0]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.149ns (logic 1.058ns (25.486%) route 3.092ns (74.514%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.847ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.799 4.149 DP/E[0] SLICE_X4Y20 FDCE r DP/s_reg_value_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 4.847 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[0]/C Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[1]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.149ns (logic 1.058ns (25.486%) route 3.092ns (74.514%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.847ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.799 4.149 DP/E[0] SLICE_X4Y20 FDCE r DP/s_reg_value_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 4.847 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[1]/C Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[2]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.149ns (logic 1.058ns (25.486%) route 3.092ns (74.514%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.847ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.799 4.149 DP/E[0] SLICE_X4Y20 FDCE r DP/s_reg_value_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 4.847 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[2]/C Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[3]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.149ns (logic 1.058ns (25.486%) route 3.092ns (74.514%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.847ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.799 4.149 DP/E[0] SLICE_X4Y20 FDCE r DP/s_reg_value_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 4.847 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[3]/C Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[4]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.149ns (logic 1.058ns (25.486%) route 3.092ns (74.514%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.847ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.799 4.149 DP/E[0] SLICE_X4Y20 FDCE r DP/s_reg_value_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 4.847 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[4]/C Slack: inf Source: write_m (input port) Destination: DP/s_reg_value_reg[6]/CE (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.149ns (logic 1.058ns (25.486%) route 3.092ns (74.514%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 4.847ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.847ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L18 0.000 0.000 r write_m (IN) net (fo=0) 0.000 0.000 write_m L18 r write_m_IBUF_inst/I L18 IBUF (Prop_ibuf_I_O) 0.934 0.934 r write_m_IBUF_inst/O net (fo=27, routed) 2.293 3.227 SM/write_m_IBUF SLICE_X2Y17 r SM/rw_reg_value[15]_i_1/I2 SLICE_X2Y17 LUT3 (Prop_lut3_I2_O) 0.124 3.351 r SM/rw_reg_value[15]_i_1/O net (fo=28, routed) 0.799 4.149 DP/E[0] SLICE_X4Y20 FDCE r DP/s_reg_value_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.506 4.847 DP/CLK SLICE_X4Y20 FDCE r DP/s_reg_value_reg[6]/C Slack: inf Source: reset (input port) Destination: DP/counter_reg[0]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 4.114ns (logic 1.101ns (26.761%) route 3.013ns (73.239%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: 4.852ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.852ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K18 0.000 0.000 f reset (IN) net (fo=0) 0.000 0.000 reset K18 f reset_IBUF_inst/I K18 IBUF (Prop_ibuf_I_O) 0.949 0.949 f reset_IBUF_inst/O net (fo=43, routed) 2.480 3.429 SM/AR[0] SLICE_X2Y17 f SM/counter[3]_i_2/I3 SLICE_X2Y17 LUT4 (Prop_lut4_I3_O) 0.152 3.581 f SM/counter[3]_i_2/O net (fo=4, routed) 0.533 4.114 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.511 4.852 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[0]/C Slack: inf Source: reset (input port) Destination: DP/counter_reg[1]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 4.114ns (logic 1.101ns (26.761%) route 3.013ns (73.239%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: 4.852ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.852ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K18 0.000 0.000 f reset (IN) net (fo=0) 0.000 0.000 reset K18 f reset_IBUF_inst/I K18 IBUF (Prop_ibuf_I_O) 0.949 0.949 f reset_IBUF_inst/O net (fo=43, routed) 2.480 3.429 SM/AR[0] SLICE_X2Y17 f SM/counter[3]_i_2/I3 SLICE_X2Y17 LUT4 (Prop_lut4_I3_O) 0.152 3.581 f SM/counter[3]_i_2/O net (fo=4, routed) 0.533 4.114 DP/counter_reg[0]_0[0] SLICE_X3Y17 FDCE f DP/counter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O net (fo=1, routed) 1.862 3.250 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 3.341 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 1.511 4.852 DP/CLK SLICE_X3Y17 FDCE r DP/counter_reg[1]/C Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: m[3] (input port) Destination: DP/rw_reg_value_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.689ns (logic 0.205ns (29.816%) route 0.483ns (70.184%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.981ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.981ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U19 0.000 0.000 r m[3] (IN) net (fo=0) 0.000 0.000 m[3] U19 r m_IBUF[3]_inst/I U19 IBUF (Prop_ibuf_I_O) 0.160 0.160 r m_IBUF[3]_inst/O net (fo=1, routed) 0.483 0.644 DP/m_IBUF[3] SLICE_X4Y19 r DP/rw_reg_value[3]_i_1/I0 SLICE_X4Y19 LUT3 (Prop_lut3_I0_O) 0.045 0.689 r DP/rw_reg_value[3]_i_1/O net (fo=1, routed) 0.000 0.689 DP/rw_out[3] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.854 1.981 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[3]/C Slack: inf Source: m[4] (input port) Destination: DP/rw_reg_value_reg[4]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.704ns (logic 0.202ns (28.681%) route 0.502ns (71.319%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.981ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.981ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R18 0.000 0.000 r m[4] (IN) net (fo=0) 0.000 0.000 m[4] R18 r m_IBUF[4]_inst/I R18 IBUF (Prop_ibuf_I_O) 0.160 0.160 r m_IBUF[4]_inst/O net (fo=1, routed) 0.502 0.662 DP/m_IBUF[4] SLICE_X4Y19 r DP/rw_reg_value[4]_i_1/I0 SLICE_X4Y19 LUT3 (Prop_lut3_I0_O) 0.042 0.704 r DP/rw_reg_value[4]_i_1/O net (fo=1, routed) 0.000 0.704 DP/rw_out[4] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.854 1.981 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[4]/C Slack: inf Source: m[7] (input port) Destination: DP/rw_reg_value_reg[7]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.707ns (logic 0.198ns (27.998%) route 0.509ns (72.002%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.981ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.981ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N17 0.000 0.000 r m[7] (IN) net (fo=0) 0.000 0.000 m[7] N17 r m_IBUF[7]_inst/I N17 IBUF (Prop_ibuf_I_O) 0.152 0.152 r m_IBUF[7]_inst/O net (fo=1, routed) 0.509 0.661 DP/m_IBUF[7] SLICE_X4Y19 r DP/rw_reg_value[7]_i_1/I0 SLICE_X4Y19 LUT3 (Prop_lut3_I0_O) 0.046 0.707 r DP/rw_reg_value[7]_i_1/O net (fo=1, routed) 0.000 0.707 DP/rw_out[7] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.854 1.981 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[7]/C Slack: inf Source: m[10] (input port) Destination: DP/rw_reg_value_reg[10]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.763ns (logic 0.223ns (29.257%) route 0.540ns (70.743%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.984ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M19 0.000 0.000 r m[10] (IN) net (fo=0) 0.000 0.000 m[10] M19 r m_IBUF[10]_inst/I M19 IBUF (Prop_ibuf_I_O) 0.178 0.178 r m_IBUF[10]_inst/O net (fo=1, routed) 0.540 0.718 DP/m_IBUF[10] SLICE_X0Y18 r DP/rw_reg_value[10]_i_1/I0 SLICE_X0Y18 LUT3 (Prop_lut3_I0_O) 0.045 0.763 r DP/rw_reg_value[10]_i_1/O net (fo=1, routed) 0.000 0.763 DP/rw_out[10] SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.857 1.984 DP/CLK SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[10]/C Slack: inf Source: m[5] (input port) Destination: DP/rw_reg_value_reg[5]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.768ns (logic 0.218ns (28.407%) route 0.550ns (71.593%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.983ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.983ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P18 0.000 0.000 r m[5] (IN) net (fo=0) 0.000 0.000 m[5] P18 r m_IBUF[5]_inst/I P18 IBUF (Prop_ibuf_I_O) 0.173 0.173 r m_IBUF[5]_inst/O net (fo=1, routed) 0.550 0.723 DP/m_IBUF[5] SLICE_X0Y19 r DP/rw_reg_value[5]_i_1/I0 SLICE_X0Y19 LUT3 (Prop_lut3_I0_O) 0.045 0.768 r DP/rw_reg_value[5]_i_1/O net (fo=1, routed) 0.000 0.768 DP/rw_out[5] SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.856 1.983 DP/CLK SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[5]/C Slack: inf Source: m[2] (input port) Destination: DP/rw_reg_value_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.772ns (logic 0.213ns (27.648%) route 0.558ns (72.352%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.981ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.981ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- V19 0.000 0.000 r m[2] (IN) net (fo=0) 0.000 0.000 m[2] V19 r m_IBUF[2]_inst/I V19 IBUF (Prop_ibuf_I_O) 0.168 0.168 r m_IBUF[2]_inst/O net (fo=1, routed) 0.558 0.727 DP/m_IBUF[2] SLICE_X4Y19 r DP/rw_reg_value[2]_i_1/I0 SLICE_X4Y19 LUT3 (Prop_lut3_I0_O) 0.045 0.772 r DP/rw_reg_value[2]_i_1/O net (fo=1, routed) 0.000 0.772 DP/rw_out[2] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.854 1.981 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[2]/C Slack: inf Source: m[0] (input port) Destination: DP/rw_reg_value_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.773ns (logic 0.210ns (27.200%) route 0.563ns (72.799%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.984ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- W19 0.000 0.000 r m[0] (IN) net (fo=0) 0.000 0.000 m[0] W19 r m_IBUF[0]_inst/I W19 IBUF (Prop_ibuf_I_O) 0.165 0.165 r m_IBUF[0]_inst/O net (fo=1, routed) 0.563 0.728 DP/m_IBUF[0] SLICE_X0Y18 r DP/rw_reg_value[0]_i_1/I0 SLICE_X0Y18 LUT3 (Prop_lut3_I0_O) 0.045 0.773 r DP/rw_reg_value[0]_i_1/O net (fo=1, routed) 0.000 0.773 DP/rw_out[0] SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.857 1.984 DP/CLK SLICE_X0Y18 FDCE r DP/rw_reg_value_reg[0]/C Slack: inf Source: m[6] (input port) Destination: DP/rw_reg_value_reg[6]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.779ns (logic 0.199ns (25.551%) route 0.580ns (74.449%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.981ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.981ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P17 0.000 0.000 r m[6] (IN) net (fo=0) 0.000 0.000 m[6] P17 r m_IBUF[6]_inst/I P17 IBUF (Prop_ibuf_I_O) 0.156 0.156 r m_IBUF[6]_inst/O net (fo=1, routed) 0.580 0.736 DP/m_IBUF[6] SLICE_X4Y19 r DP/rw_reg_value[6]_i_1/I0 SLICE_X4Y19 LUT3 (Prop_lut3_I0_O) 0.043 0.779 r DP/rw_reg_value[6]_i_1/O net (fo=1, routed) 0.000 0.779 DP/rw_out[6] SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.854 1.981 DP/CLK SLICE_X4Y19 FDCE r DP/rw_reg_value_reg[6]/C Slack: inf Source: m[14] (input port) Destination: DP/rw_reg_value_reg[14]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.790ns (logic 0.210ns (26.575%) route 0.580ns (73.425%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.983ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.983ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N19 0.000 0.000 r m[14] (IN) net (fo=0) 0.000 0.000 m[14] N19 r m_IBUF[14]_inst/I N19 IBUF (Prop_ibuf_I_O) 0.162 0.162 r m_IBUF[14]_inst/O net (fo=1, routed) 0.580 0.742 DP/m_IBUF[14] SLICE_X0Y19 r DP/rw_reg_value[14]_i_1/I0 SLICE_X0Y19 LUT3 (Prop_lut3_I0_O) 0.048 0.790 r DP/rw_reg_value[14]_i_1/O net (fo=1, routed) 0.000 0.790 DP/rw_out[14] SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.856 1.983 DP/CLK SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[14]/C Slack: inf Source: m[15] (input port) Destination: DP/rw_reg_value_reg[15]/D (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 0.791ns (logic 0.200ns (25.237%) route 0.592ns (74.763%)) Logic Levels: 2 (IBUF=1 LUT3=1) Clock Path Skew: 1.983ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.983ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N18 0.000 0.000 r m[15] (IN) net (fo=0) 0.000 0.000 m[15] N18 r m_IBUF[15]_inst/I N18 IBUF (Prop_ibuf_I_O) 0.155 0.155 r m_IBUF[15]_inst/O net (fo=1, routed) 0.592 0.746 DP/m_IBUF[15] SLICE_X0Y19 r DP/rw_reg_value[15]_i_2/I0 SLICE_X0Y19 LUT3 (Prop_lut3_I0_O) 0.045 0.791 r DP/rw_reg_value[15]_i_2/O net (fo=1, routed) 0.000 0.791 DP/rw_out[15] SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r W5 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 clk W5 r clk_IBUF_inst/I W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O net (fo=1, routed) 0.685 1.099 clk_IBUF BUFGCTRL_X0Y0 r clk_IBUF_BUFG_inst/I BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O net (fo=46, routed) 0.856 1.983 DP/CLK SLICE_X0Y19 FDCE r DP/rw_reg_value_reg[15]/C