ECE448 Lab 1

Lab 1

Developing Effective Testbenches.
Simulation using Xilinx Vivado Simulator.

Lecture slides:

Lab Lecture 1

To print N slides per page, please choose Print, Options:


Xilinx Vivado Installation Instructions

Lab 1 Examples:

Example 1:

Testbench: sevenSegment_TB.vhd    DUV: sevenSegment.vhd 

Example 2:

Testbench: sequential_divider_tb.vhd    DUV: sequential_divider.vhd   reg.vhd   shift_reg.vhd 

Lab 1 Exercise:

    Lab Exercise:  Specification   ALU_psm_1.vhd  ALU_psm_2.vhd  

Lab 1 Files:

Lab1_psm_1.vhd, Lab1_psm_2.vhd


Please email your corrections and suggestions to Kris Gaj