Lab 2

Implementing and Synthesizing Combinational Logic in VHDL

Lecture slides:

Lab Lecture 2

To print N slides per page, please choose Print, Options:

• Print what: Handouts,
• Handouts: Slides per page: N

Example:

    Synthesizable code: sequential_divider.vhd  shift_reg.vhd  reg.vhd

    Testbench: sequential_divider_tb.vhd

Lab 2 Task 1 Block Diagram (can be modified using draw.io after storing on your hard drive using right click - Download Linked File As...):

    MUL_by_SQR.drawio

Lab 2 Exercise:

  Specification  

Please email your corrections and suggestions to Kris Gaj.