Lab 3

Implementing and Synthesizing Sequential Logic in VHDL

Lecture slides:

Lab Lecture 3

To print N slides per page, please choose Print, Options:

• Print what: Handouts,
• Handouts: Slides per page: N

Example:

    Synthesizable code: sequential_divider.vhd  shift_reg.vhd  reg.vhd

    Testbench: sequential_divider_tb.vhd

    Constraints: sequential_divider.xdc

Lab 3 Main Task Block Diagram (can be modified using draw.io after storing on your hard drive using right click - Download Linked File As...):

    SEQ_UMUL_k.drawio

Lab 3 Exercise:

  Specification  

Please email your corrections and suggestions to Kris Gaj.