ECE448 Lab 2

Lab 3

Implementing and Synthesizing Sequential Logic in VHDL

Lecture slides:

Lab Lecture 3

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    Synthesizable code: sequential_divider.vhd  shift_reg.vhd  reg.vhd

    Testbench: sequential_divider_tb.vhd

    Constraints: sequential_divider.xdc

Lab 3 Main Task Block Diagram (can be modified using after storing on your hard drive using right click - Download Linked File As...):


Lab 3 Exercise:


Please email your corrections and suggestions to Kris Gaj