Music Theater Building, room 1002
Face-to-face: Mondays, 6:00-7:00 PM, or by appointment, ENGR 3225.
Using Zoom: Please send an e-mail request or private Piazza request, including your availability in the form of a list of days and time slots suitable for you. I will select one particular day and starting time of the meeting,
and I will send you the corresponding Zoom link. During the conference call, please make sure to have your camera on and the ability to share your screen.
Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and
controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis, and performance optimization.
Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly
Pong P. Chu, RTL Hardware Design Using VHDL: Coding for
Efficiency, Portability, and Scalability, Wiley-IEEE Press,
Ricardo Jasinski, Effective
Coding with VHDL: Principles and Best Practice, 1st Edition, The
MIT Press, 2016.
Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer,
Parallel Programming for FPGAs: The HLS Book, 2018.
Software Packages Used in This Class
FREE versions can be installed on your laptops and home workstations.
Course Outline (subject to possible modifications):
- Organization of the Course. Introduction to FPGA Technology. Project. 08/22/2022
- Digital Logic Refresher - Combinational Logic. 08/29/2022
- Digital Logic Refresher - Sequential Logic. 09/12/2022
- RTL Design Methodology - Part 1. 09/19/2022
- RTL Design Methodology - Part 2. 09/26/2022
- VHDL Fundamentals. 10/03/2022
- Testbenches. 10/11/2022
- Dataflow Modeling in VHDL. VHDL Description of Basic Combinational Building Blocks. 10/17/2022
- VHDL Description of Basic Sequential Building Blocks. Poor Design Practices & Their Remedies. 10/24/2022
- Midterm Exam. 10/31/2022
- Modeling of Circuits with Regular Structure. Timing Analysis. 11/07/2022
- Solutions to the Midterm Exam. Class Exercise on Timing Analysis. Design of Controllers - Part A. 11/14/2022
- Design of Controllers - Part B. 11/21/2022
- FPGA Memories. VHDL-2008. Follow-Up Courses. 11/28/2022
- Final Exam (7:30-10:15 PM). 12/12/2022
In consultation with the instructor, you will have an option to select between
- One semester-long project
- Can be done in groups of 1-2 students
- Different for each group
- Proposed by the instructor or students
- Based on the specification developed by members of the group and approved by the instructor
- Can be related to your MS Thesis, Ph.D. Dissertation, or Senior Design Project
- Can be combined with a project in ECE 646 Applied Cryptography, taught by Dr. Kaps
- Can include practical experiments performed using FPGA or FPGA SoC boards
- Best projects rewarded with bonus points
- Three smaller projects
- Done individually
- The same for all students choosing this option
- Specified by the instructor
- Each about 2-3 weeks long
- May be related to one another
- Contest for the best design
- Only fully verified designs eligible for an award
- Designs ranked in terms of speed (design with the shortest execution time ranked first).
This year's projects proposed by the instructor may involve implementing basic building blocks of
- Post-Quantum Cryptography
- Lightweight Cryptography
These projects will support standardization organizations, such as the National Institute of Standards and Technology (NIST), in the selection of new cryptographic standards.
Deliverables for Type 1 Projects
Detailed Block Diagrams
Reduced Complexity Block Diagrams
Examples of GMU Designs - LWC Candidates
Examples of GMU Designs - PQC Building Blocks
Examples of GMU Designs - Hash Functions
Using Vivado for Synthesis, Implementation, and Timing Analysis
Homework 5 - bonus, due Wednesday, November 30, 2022, 11:59 PM
Homework 4b, required for all students; due Saturday, November 5, 2022, 11:59 PM
Homework 4a + Related Testbenches [testbench_examples.zip], optional for students with experience in using Xilinx Vivado; recommended to be completed by Wednesday, November 2, 2022
Homework 3, due Saturday, October 8, 2022, 11:59 PM
Homework 2, due Wednesday, September 21, 2022, 11:59 PM
Homework 1, due Saturday, September 10, 2022, 11:59 PM
Homework assignments will be posted gradually here, at least 7 days before a given assignment is due.
Please submit all solutions using the Blackboard section ECE-545-001 (Fall 2022).
All solutions should be submitted in electronic form. When preparing your hand-drawn/hand-written solutions for submission, please use either a scanner app on your smartphone or an "old-fashioned" scanner (often integrated with your printer). Please do not submit photos; they are usually hard to read and take a lot of space. You can also use a tablet, such as an iPad, to directly write down and save your solutions in electronic form.
Each student can have an automatic 72-hour extension on one assignment (no questions asked) as long as the student informs the instructor in writing.
Any additional late assignments will earn a flat 20% grade deduction as long as they are completed within 7 days of the deadline.
For selected assignments, you will have an opportunity to submit a revised version of your solutions due a week after receiving your graded homework. Your final score for the assignment will be an average of your first and second scores.
Lecture 16: VHDL-2008 : see Piazza under Resources => Resources => Lecture Notes
Lecture 15: FPGA Memories. [pdf-1, pdf-6]
Lecture 14: Design of Controllers - Part B. [pdf-1, pdf-6]
Lecture 13: Design of Controllers - Part A. [pdf-1, pdf-6]
Midterm Exam - Problem 1
Lecture 12: Timing Analysis. [pdf-1, pdf-6]
Lecture 11: Modeling of Circuits with Regular Structure. [pdf-1, pdf-6]
Lecture 10: VHDL Description of Basic Sequential-Circuit Building Blocks. Poor Design Practices & Their Remedies. [pdf-1, pdf-6]
Lecture 9: VHDL Description of Basic Combinational-Circuit Building Blocks. [pdf-1, pdf-6]
Lecture 8: Dataflow Modeling in VHDL. [pdf-1, pdf-6]
Lecture 7: Testbenches. [pdf-1, pdf-6]
Lecture 6: VHDL Fundamentals. [pdf-1, pdf-6]
Homework 2, Problem 3 - discussion. [pdf-1]
Lecture 5: RTL Design Methodology - Part B. [pdf-1, pdf-6]
Lecture 4: RTL Design Methodology - Part A. [pdf-1, pdf-6]
Lecture 3: Digital Logic Refresher. Part B - Sequential Logic Building Blocks. [pdf-1, pdf-6]
Lecture 2: Digital Logic Refresher. Part A - Combinational Logic Building Blocks. [pdf-1, pdf-6]
Lecture 1: Organization of the Course. Introduction to FPGA Technology. Project. [pdf-1, pdf-6]
Lecture 1 Appendix: Quantum Computers and Cryptography. [pdf-1, pdf-6]
Viewgraphs will be posted gradually here.
VHDL Instructions: Templates
HDL Modeling Guidelines
Recommended Block Diagram Editors
Past Course Web Pages
Practice and Past Exams
Solutions to the Final Exam 2018: