# Kris Gaj

### Books and Proceedings

- C. Marchand, L. Bossuet, and K. Gaj, "Ultra-Lightweight Implementation in Area of Block Ciphers,"
in L. Bossuet and L. Torres (Eds.),
*Foundations of Hardware IP Protection*, Springer International Publishing, pp. 117-203, 2017.

- C. Clavier and K. Gaj (Eds.), Cryptographic Hardware and
Embedded Systems - CHES 2009, 11th International Workshop,
Lausanne, Switzerland, September 6-9, 2009, Proceedings,
Series: Lecture Notes in Computer Science, Subseries: Security
and Cryptology, vol. 5747, Sep. 2009. ISBN: 978-3-642-04137-2.

- K. Gaj and P. Chodowiec, "FPGA and ASIC Implementations of
AES," Chapter 10 in C.K. Koc (Ed.), Cryptographic Engineering, pp. 235-320,
Springer, Dec. 2008. ISBN-10: 0387718168. ISBN-13:
978-0387718163.

- K. Gaj, The Enigma Cipher:
Methods of Breaking, Transport and Communications
Press, Warsaw, Poland (in Polish).

### Journal and Peer-Review Conference Publications

- L. Beckwith, R. Wallace, K. Mohajerani, and K. Gaj ,
"A High-Performance Hardware Implementation of the LESS Digital Signature Scheme,"
in 14th International Conference on Post-Quantum Cryptography, PQCrypto 2023, Springer, LNCS 14154, pp. 57–90, College Park, MD, Aug. 2023
(published version).

- D.T. Nguyen and K. Gaj,
"Fast Falcon Signature Generation and Verification Using ARMv8 NEON Instructions,"
in 14th International Conference on Cryptology, AFRICACRYPT 2023, Springer, LNCS 14064, pp. 417-441, Sousse, Tunisia, July 2023
(published version).

- J. Hu, W. Wang, K. Gaj, L. Wang, H. Wang,
"Engineering Practical Rank-Code-Based Cryptographic Schemes on Embedded Hardware. A Case Study on ROLLO,"
IEEE Transactions on Computers, vol. 72, no. 7, July 1, 2023, pp. 2094-2110
(published version).

- V.B. Dang, K. Mohajerani, and K. Gaj,
"High-Speed Hardware Architectures and FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber,"
IEEE Transactions on Computers, vol. 72, no. 2, Feb. 1, 2023, pp. 306-320
(published version).

- L. Beckwith, D.T. Nguyen, and K. Gaj,
"High-Performance Hardware Implementation of CRYSTALS-Dilithium,"
in 2021 International Conference on Field-Programmable Technology, FPT 2021, Dec. 2021
(accepted version).

- A. Abdulgadir, K. Mohajerani, V.B. Dang, J.-P. Kaps, and K. Gaj,
"A Lightweight Implementation of Saber Resistant Against Side-Channel Attacks,"
in 22nd International Conference on Cryptology in India, Indocrypt 2021, Jaipur, India, Dec. 2021
(accepted version).

- D.T. Nguyen and K. Gaj,
"Fast NEON-based multiplication for lattice-based NIST Post-Quantum Cryptography finalists,"
in 12th International Conference on Post-Quantum Cryptography, PQCrypto 2021, Springer, LNCS 12841, pp. 234-254, July 2021
(accepted version
+ slides short
+ slides long).

- K. Mohajerani, R. Haeussler, R. Nagpal, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj,
"Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security,"
in 31st ACM Great Lakes Symposium on VLSI, GLSVLSI 2021, pp. 229-234, Jun. 2021
(accepted version).

- K. Mohajerani, R. Haeussler, R. Nagpal, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj,
"Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process,"
in 24th Design, Automation and Test in Europe Conference, DATE 2021, Feb. 2021
(accepted version).

- J. Bahrami, V.B. Dang, A. Abdulgadir, K.N. Khasawneh, J.-P. Kaps, and K. Gaj,
"Lightweight Implementation of the LowMC Block Cipher Protected Against Side-Channel Attacks,"
in 4th Workshop on Attacks and Solutions in Hardware Security, ASHES 2021, Nov. 2020
(accepted version).

- M. Andrzejczak and K. Gaj,
"A Multiplatform Parallel Approach for Lattice Sieving Algorithms,"
in International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2020, Oct. 2020.

- J. Xie, K. Basu, K. Gaj, and U. Guin,
"Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography,"
in 2020 IEEE 38th VLSI Test Symposium, VTS 2020
(accepted version).

- D.T. Nguyen, V.B. Dang, and K. Gaj,
"High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-based Post-Quantum Cryptography using Software/Hardware Codesign,"
in 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, LNCS 12083, pp. 247-257
(accepted version).

- M.X. Lyons and K. Gaj,
"Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography,"
in 23rd Design, Automation and Test in Europe Conference, DATE 2020
(accepted version).

- V.B. Dang, F. Farahmand, M. Andrzejczak, and K. Gaj,
"Implementing and Benchmarking Three Lattice-based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign,"
in 2019 International Conference on Field Programmable Technology, FPT 2019,
Tianjin, China, Dec. 11-13, 2019, pp. 206-214
(accepted version
+ slides).

- M. Andrzejczak, F. Farahmand, and K. Gaj,
"Full Hardware Implementation of the Post-Quantum Public-Key Cryptography Scheme Round5,"
in 2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019,
Cancun, Mexico, Dec. 9-11, 2019
(accepted version).

- K. Zamiri-Azar, F. Farahmand, H.M. Kamali, S. Roshanisefat,
H. Homayoun, W. Diehl, K. Gaj, and A. Sasan,
"COMA: Communication and Obfuscation Management Architecture,"
in 22nd International Symposium on Research in Attacks, Intrusions and
Defenses, RAID 2019, Beijing, China, Sep. 23-25, 2019.

- F. Farahmand, D.T. Nguyen, V.B. Dang, A. Ferozpuri, and K. Gaj,
"Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt
Using High-Level Synthesis and Register-Transfer Level Design Methodologies,"
in 29th International Confererence on Field-Programmable Logic and Applications,
FPL 2019, Barcelona, Spain, Sep. 9-13, 2019 (accepted version + poster).

- T. Winograd, R. Shahid and K. Gaj,
"An Automated Scheduler-based Approach for the Development of Cryptoprocessors
for Pairing-Based Cryptosystems,"
in 26th Reconfigurable Architectures Workshop,
RAW 2019, Rio de Janeiro, Brazil, May 20, 2019
(accepted version
+ slides).

- F. Farahmand, V.B. Dang, D.T. Nguyen, and K. Gaj,
"Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key
Encapsulation Mechanisms Using Software/Hardware Codesign,"
in 10th International Conference on Post-Quantum Cryptography,
PQCrypto 2019, Chongqing, China, May 8-10, 2019, Lecture Notes in Computer Science, vol. 11505, Springer, pp. 23-43
(paper + slides).

- F. Farahmand, M. U. Sharif, K. Briggs, and K. Gaj,
"A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES,"
in 2018 International Conference on Field Programmable Technology, FPT 2018,
Naha, Okinawa, Japan, Dec. 10-14, 2018
(extended ePrint version
+ accepted version
+ slides).

- W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj,
"Face-off between the CAESAR Lightweight Finalists: ACORN vs. Ascon,"
in 2018 International Conference on Field Programmable Technology, FPT 2018,
Naha, Okinawa, Japan, Dec. 10-14, 2018
(extended ePrint version
+ accepted version
+ poster).

- A. Ferozpuri and K. Gaj, "High-Speed FPGA Implementation of the NIST Round 1
Rainbow Signature Scheme," in 2018 International Conference on Reconfigurable
Computing and FPGAs, ReConFig 2018, Cancun, Mexico, Dec. 3-5, 2018
(slides).

- T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, H. Homayoun,
"Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering".
ACM Transactions on Design Automation of Electronic Systems, Special issue on Internet of Things System Performance, Reliability, and Security,
vol. 23, no. 6, Dec. 2018.
(paper).

- G. Banegas, P. S. L. M. Barreto, B. O. Boidje, P.-L. Cayrel, G. N. Dione, K. Gaj,
C. T. Gueye, R. Haeussler, J. B. Klamti, O. Ndiaye, D. T. Nguyen, and E. Persichetti,
"DAGS: Key Encapsulation Using Dyadic GS codes," Journal of Mathematical Cryptology,
vol. 12, no. 4, pp. 221–240, Dec. 2018
(paper).

- W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps and K. Gaj,
"Fixing the CLOC with Fine-grain Leakage Analysis,"
in 2nd Workshop on Attacks and Solutions in Hardware Security, ASHES 2018,
Toronto, ON, Canada, Oct. 19, 2018, pp. 75-80
(paper
+ slides).

- W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps and K. Gaj,
"Comparison of Cost of Protection against Differential Power Analysis of
Selected Authenticated Ciphers," Cryptography, vol. 2, no. 3, Sep. 2018
(paper).

- H.M. Kamali, K. Zamiri-Azar, K. Gaj, H. Homayoun, and A. Sasan,
"LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and
ASIC-Hardware Protection," in 2018 IEEE Computer Society Annual Symposium on VLSI,
ISVLSI 2018, Hong Kong SAR, China, July 8-11, pp. 405-410
(arXiv version)
.

- S. Roshanisefat, H.K. Thirumala, K. Gaj, H. Homayoun, and A. Sasan,
"Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating
Obfuscation Schemes," in 24th IEEE International Symposium on On-Line Testing
and Robust System Design, IOLTS 2018, Costa Brava, Spain, July 2-4, 2018, pp. 275-280
(arXiv version)
.

- K. Gaj, "Challenges and Rewards of Implementing and Benchmarking Post-Quantum
Cryptography in Hardware," in 28th ACM Great Lakes Symposium on VLSI, GLSVLSI 2018,
Chicago, IL, USA, May 23-25, 2018, pp. 359-364
(paper
+ slides).

- W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj,
"Comparison of Cost of Protection Against Differential Power Analysis of
Selected Authenticated Ciphers,"
in IEEE International Symposium on Hardware Oriented Security and Trust,
HOST 2018, Washington, DC, Apr. 30-May 4, 2018, pp. 147-152
(extended ePrint version
+ accepted version
+ poster).

- F. Farahmand, W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj,
"Improved Lightweight Implementations of CAESAR Authenticated Ciphers,"
in 26th IEEE International Symposium on Field-Programmable Custom Computing Machines,
FCCM 2018, Boulder, CO, USA, IEEE, pages 29–36, Apr. 29-May 1, 2018, pp. 29-36
(extended ePrint version
+ accepted version
+ slides).

- W. Diehl, A. Abdulgadir, J.-P. Kaps and K. Gaj,
"Comparing the Cost of Protecting Selected Lightweight Block Ciphers against
Differential Power Analysis in Low-Cost FPGAs," Computers, vol. 7, no. 28, Apr. 2018
(paper).

- E. Homsirikamol and K. Gaj, "Toward a New HLS-Based Methodology for FPGA Benchmarking
of Candidates in Cryptographic Competitions: The CAESAR Contest Case Study,"
in 2017 International Conference on Field Programmable Technology - FPT 2017,
Melbourne, Australia, Dec. 11-13, 2017, pp. 120-127
(accepted version
+ slides).

- W. Diehl, A. Abdulgadir, J.-P. Kaps and K. Gaj, "Comparing the Cost of Protecting
Selected Lightweight Block Ciphers Against Differential Power Analysis in Low-Cost FPGAs,"
in 2017 International Conference on Field Programmable Technology - FPT 2017,
Melbourne, Australia, Dec. 11-13, 2017, pp. 128-135
(paper
+ slides).

- B. Jarvis and K. Gaj, "Selection of an Error-Correcting Code for FPGA-based Physical
Unclonable Functions," in 2017 International Conference on Field Programmable Technology - FPT 2017,
Melbourne, Australia, Dec. 11-13, 2017, pp. 243-246
(paper
+ poster).

- W. Diehl, A. Abdulgadir, J.-P. Kaps and K. Gaj, "Side-channel Resistant Soft Core
Processor for Lightweight Block Ciphers," in 2017 International Conference on
Reconfigurable Computing and FPGAs - ReConFig 2017, Cancun, Mexico, Dec. 4-6, 2017
(paper
+ slides).

- A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps and K. Gaj,
"A Scalable ECC Processor Implementation for High-Speed and Lightweight with
Side-Channel Countermeasures," in 2017 International Conference on
Reconfigurable Computing and FPGAs - ReConFig 2017, Cancun, Mexico, Dec. 4-6, 2017
(paper
+ slides).

- F. Farahmand, A. Ferozpuri, W. Diehl and K. Gaj,
"Minerva: Automated Hardware Optimization Tool," in 2017 International Conference on
Reconfigurable Computing and FPGAs - ReConFig 2017, Cancun, Mexico, Dec. 4-6, 2017
(accepted version
+ poster).

- W. Diehl, F. Farahmand, P. Yalla, J.-P. Kaps and K. Gaj
"Comparison of Hardware and Software Implementations of Selected Lightweight
Block Ciphers," 27th International Conference on Field Programmable Logic and
Applications, FPL 2017, Ghent, Belgium, Sep. 4-8, 2017
(accepted version
+ poster).

- S. Deshpande and K. Gaj, "Analysis and Inner-Round Pipelined Implementation of
Selected Parallelizable CAESAR Competition Candidates," 19th Euromicro Conference
on Digital System Design - DSD 2017, Vienna, Austria, Aug. 30-Sep. 1, 2017
(accepted version
+ slides).

- B. Habib, J.-P. Kaps, and K. Gaj, "Implementation of Efficient SR-Latch PUF on
FPGA and SoC Devices," Microprocessors and Microsystems, vol. 53, Aug. 2017, pp. 92-105
(paper).

- W. Diehl and K. Gaj, "RTL Implementations and FPGA Benchmarking of Selected CAESAR
Round Two Authenticated Ciphers," Microprocessors and Microsystems, vol. 52, July 2017,
pp. 202-218
(paper).

- B. Habib and K. Gaj, "A Comprehensive Set of Schemes for PUF Response Generation,"
Microprocessors and Microsystems, vol. 51, June 2017, pp. 239-251
(paper).

- R. Shahid, T. Winograd, and K. Gaj, "A Generic Approach to the Development of
Coprocessors for Elliptic Curve Cryptosystems," 24th Reconfigurable Architectures
Workshop, Orlando, Florida, USA, May 29-30, 2017
(accepted version
+ slides).

- C. Marchand, L. Bossuet, and K. Gaj, "Area-oriented Comparison of Lightweight Block Ciphers Implemented in Hardware for the Activation Mechanism in the Anti-counterfeiting Schemes,"
International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp. 274-291, Feb. 2017
(paper).

- E. Homsirikamol and K. Gaj, "AEZ: Anything-but EaZy in Hardware," 17th International Conference on Cryptology in India - Indocrypt 2016, Kolkata, India, Dec. 11-14, 2016.
(accepted version +
slides)

- F. Farahmand, E. Homsirikamol, and K. Gaj, "A Zynq-based Testbed for the Experimental Benchmarking of Algorithms Competing in Cryptographic Contests," 2016 International Conference
on Reconfigurable Computing and FPGAs, ReConFig 2016,
Cancun, Mexico, Nov. 30-Dec. 2, 2016.
(accepted version
+ poster
+ short talk)

- M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj,
"Hardware-Software Codesign of RSA for Optimal Performance vs. Flexibility Trade-off,"
26th International Conference on Field Programmable Logic and Applications, FPL 2016,
Lausanne, Switzerland, Aug. 29-Sep. 2, 2016.
(accepted version
+ poster
+ short talk)

- W. Diehl and K. Gaj, "RTL Implementations and FPGA Benchmarking of Three Authenticated
Ciphers Competing in CAESAR Round Two," 19th Euromicro Conference on Digital System Design
- DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016.
(accepted version +
slides)

- W. Diehl and K. Gaj, "Implementation of a Boolean Masking Scheme for the SCREAM Cipher,"
19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus,
Aug. 31-Sep. 2, 2016.
(accepted version
+ poster)

- T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun,
"Hybrid STT-CMOS Designs for Reverse-engineering Prevention,"
ACM/IEEE 53rd Design Automation Conference, DAC 2016,
Austin, TX, June 18-22, 2016
(paper
+ slides).

- B. Habib and K. Gaj, "A Comprehensive Set of Schemes for PUF Response Generation,"
LNCS 9625, 12th International Symposium, ARC 2016, Mangaratiba, Rio de Janeiro, Brazil,
Mar. 21-24, 2016, pp. 183-194.
(accepted version
+ slides)

- E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, "A Universal Hardware API for Authenticated Ciphers," 2015 International Conference
on Reconfigurable Computing and FPGAs, ReConFig 2015,
Mayan Riviera, Mexico, Dec. 7-9, 2015.
(accepted version + slides)

- T. Dakve, J. Hiney, K. Szczypiorski, and K. Gaj, "Using Facebook for Image Steganography,"
Fourth International Workshop on Cyber Crime (IWCC 2015),
co-located with 10th International Conference on Availability,
Reliability and Security (ARES 2015), Toulouse, France, Aug. 24-25, 2015.
(accepted version)

- E. Homsirikamol and K. Gaj, "Hardware Benchmarking of Cryptographic Algorithms
Using High-Level Synthesis Tools: The SHA-3 Contest Case Study," in LNCS 9040,
Applied Reconfigurable Computing, 11th International Symposium, ARC 2015,
Bochum, Germany, Apr. 13-17, 2015, pp. 217-228.
(accepted version)

- B. Habib, J.-P. Kaps, and K. Gaj, "Efficient SR-Latch PUF,"
in LNCS 9040, Applied Reconfigurable Computing, 11th International Symposium, ARC 2015,
Bochum, Germany, Apr. 13-17, 2015, pp. 205-216.
(accepted version + slides)

- E. Homsirikamol and K. Gaj, "Can High-Level Synthesis Compete Against a Hand-Written
Code in the Cryptographic Domain? A Case Study," 2014 International Conference
on Reconfigurable Computing and FPGAs, ReConFig 2014,
Cancun, Mexico, Dec. 8-10, 2014.
(accepted version + slides)

- P. Morawiecki, K. Gaj, E. Homsirikamol, K. Matusiewicz, J.
Pieprzyk, M. Rogawski, M. Srebrny, and M. Wojcik, "ICEPOLE: High-speed,
Hardware-oriented Authenticated Encryption," in LNCS 8731,
Cryptographic Hardware and Embedded Systems - CHES 2014, Busan, South
Korea, Sep. 23-26, 2014, pp. 392-413. (accepted version + slides)

- M. Rogawski, E. Homsirikamol, and K. Gaj, "A Novel Modular Adder
for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs,"
24th
International Conference on Field Programmable Logic and
Applications, FPL 2014, Munich, Germany, Sep. 2-4, 2014. (accepted version + slides)

- M. Rogawski, K. Gaj, E. Homsirikamol, "A High-Speed Unified
Hardware Architecture for 128 and 256-bit Security Levels of AES
and the SHA-3 Candidate Groestl," Microprocessors and
Microsystems - Embedded Hardware Design, vol. 37, no. 6-7,
Aug.-Oct. 2013, pp. 572-582
(paper).

- B. Habib, K. Gaj and J.-P. Kaps, "FPGA PUF based on
Programmable LUT Delays," in 16th Euromicro Conference on
Digital System Design - DSD 2013, Santander, Spain, Sep. 2013,
pp. 697-704 (accepted version + slides).

- B. Brewster, E. Homsirikamol, R. Velegalati, K. Gaj, "Option
Space Exploration Using Distributed Computing for Efficient
Benchmarking of FPGA Cryptographic Modules," in 2012
International Conference on Field Programmable Technology - FPT
2012, Seoul, Korea, Dec. 2012, pp. 113-118 (accepted version + poster).
Copyright 2012 IEEE. See the IEEE Copyright Notice below.

- S. Paul, E. Homsirikamol, and K. Gaj, "A Novel
Permutation-based Hash Mode of Operation FP and The Hash
Function SAMOSA," in LNCS 7668, INDOCRYPT 2012, 13th International Conference on Cryptology
in India, Kolkata, India, Dec. 2012, pp. 509-527 (extended ePrint version + slides).

- M. Rogawski and K. Gaj, "A High-Speed Unified Hardware
Architecture for AES and the SHA-3 Candidate Groestl", in 15th
Euromicro Conference on Digital System Design - DSD 2012, Cesme,
Izmir, Turkey, Sep. 2012 (paper + slides).

- R. Shahid, U. Sharif, M. Rogawski, and K. Gaj, "Use of
Embedded FPGA Resources in Implementations of 14 Round 2 SHA-3
Candidates," in 2011 International Conference on Field
Programmable Technology - FPT 2011, New Delhi, India, Dec. 2011, pp. 1-9.
(slides + accepted
version) Copyright 2011 IEEE. See the IEEE Copyright Notice below.

- E. Homsirikamol, M. Rogawski, and K. Gaj, "Throughput vs. Area
Trade-offs in High-Speed Architectures of Five Round 3 SHA-3
Candidates Implemented Using Xilinx and Altera FPGAs," in LNCS
6917, Cryptographic Hardware and Embedded Systems - CHES 2011,
Nara, Japan, Sep. 28-Oct. 1, pp. 491-506. (paper +
slides)

- M. Huang, K. Gaj, and T. El-Ghazawi, "New Hardware
Architectures for Montgomery Modular Multiplication Algorithm,"
IEEE Transactions on Computers, vol. 60, no. 7, July 2011, pp.
923-936. (abstract
+ accepted
version) Copyright 2011 IEEE. See the IEEE Copyright Notice below.

- K. Gaj and R. Steinwandt, "Editorial: Hardware Architectures
for Algebra, Cryptology, and Number Theory," Integration, the
VLSI Journal, vol. 44, no. 4, Sep. 2011, pp. 257-258 (paper).

- K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M.
Khaleeluddin, R. Bachimanchi, and M. Rogawski, "Area-Time
Efficient Implementation of the Elliptic Curve Method of
Factoring in Reconfigurable Hardware for Application in the
Number Field Sieve," IEEE Transactions on Computers, vol. 59,
no. 9, Sep. 2010, pp. 1264-1280. (abstract
+ accepted
version) Copyright 2010 IEEE. See the IEEE Copyright Notice below.

- K. Gaj, J.-P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol,
B.Y. Brewster, "ATHENa – Automated Tool for Hardware EvaluatioN:
Toward Fair and Comprehensive Benchmarking of Cryptographic
Hardware using FPGAs," 20th International Conference on Field
Programmable Logic and Applications, Milano, Italy, Aug. 31st -
Sep. 2nd, 2010 (best paper FPL
Community award) (slides + abstract
+ accepted
version) Copyright 2010 IEEE. See the IEEE Copyright Notice below.

- K. Gaj, E. Homsirikamol, and M. Rogawski, "Fair and
Comprehensive Methodology for Comparing Hardware Performance of
Fourteen Round Two SHA-3 Candidates Using FPGAs," in LNCS 6225,
Cryptographic Hardware and Embedded Systems - CHES 2010, Santa
Barbara, CA, USA, Aug. 2010, pp. 264-278 (paper +
slides).

- C. Shu, S. Kwon, and K. Gaj, "Reconfigurable Computing
Approach for Tate Pairing Cryptosystems over Binary Fields", IEEE Transactions on Computers,
vol. 58, no. 9, pp. 1221-1237, Sep. 2009. (abstract
+ accepted version)
Copyright 2009 IEEE. See the IEEE Copyright Notice below.

- B. Zhou, Y. Peng, K. Gaj, Z. Zhou, "Implementation and Comparative Analysis of AES as a Stream Cipher,"
2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, Aug. 2009, pp. 396-400.
(paper)

- R. Vaslin, G. Gogniat, J.-P. Diguet, R. Tessier, D.
Unnikrishnan, and K. Gaj, "Memory security management for
reconfigurable embedded systems," Proc. International Conference
on Field Programmable Technology, FPT 2008, Taipei, Dec. 2008, pp. 153-160.
(paper)

- P. Saha, E. El-Araby, M. Huang, M. Taher, S. Lopez-Buedo, T.
El-Ghazawi, C. Shu, K. Gaj, A. Michalski, and D. Buell,
"Portable Library Development for Reconfigurable Computing
Systems: A Case Study",
*Elsevier Parallel Computing: Systems & Applications*, vol. 34, issues 4+5, pp. 245-260, May 2008. ISSN: 0167-8191. (paper)

- M. Huang, K. Gaj, S. Kwon, and T. El-Ghazawi, "An Optimized
Hardware Architecture for the Montgomery Multiplication
Algorithm," Proc. 11th International Workshop on Practice and
Theory in Public Key Cryptography, PKC 2008, Barcelona, Spain,
pp. 214-228, Mar. 2008. (paper
+ slides)

- T. El-Ghazawi, E. El-Araby, M. Huang, K. Gaj, V. Kindratenko,
D. Buell, "The Promise of High-Performance Reconfigurable
Computing," Computer, vol. 41, no. 2, pp. 69-76, Feb. 2008. (paper)

- D. Hwang, M. Chaney, S. Karanam, N. Ton, and K. Gaj,
"Comparison of FPGA-targeted hardware implementations of eSTREAM
stream cipher candidates," Proc. State of the Art of Stream
Ciphers Workshop, SASC 2008, Lausanne, Switzerland, pp. 151-162,
Feb. 2008. (paper +
slides)

- C. Shu, S. Kwon, K. Gaj, "FPGA Accelerated Multipliers over Binary Composite Fields
Constructed via Low Hamming Weight Irreducible Polynomials"
IET Computers and Digital Techniques, vol. 2, no. 1, Jan. 2008, pp. 6-11.
(paper)

- G. Southern, C. Mason, L. Chikkam, P. Baier, and K. Gaj, "FPGA
Implementation of High Throughput Circuit for Trial Division by
Small Primes," Proc. Special Purpose Hardware for Attacking
Cryptographic Systems, SHARCS 2007, Vienna, Austria, Sep. 2007.
(paper
+ slides)

- A. Abusharekh and K. Gaj, "Comparative Analysis of Software
Libraries for Public Key Cryptography," Proc. Software
Performance Enhancement for Encryption and Decryption, SPEED
2007, Amsterdam, the Netherlands, June 2007, pp. 3-19. (paper +
slides)

- D. Buell, T. El-Ghazawi, K. Gaj, V. Kindratenko,
"Guest Editors' Introduction: High-Performance Reconfigurable Computing," Computer Magazine, special issue, Mar. 2007
(paper).

- M. Huang, T. El-Ghazawi, B. Larson, and K. Gaj,
"Development of Block-Cipher Library for Reconfigurable Computers,"
Proc. 3rd Southern Conference on Programmable Logic, SPL 2007, Mar del Plata, Argentina, Feb. 2007,
pp. 191-194. (paper)

- K. Gaj, G. Southern and R. Bachimanchi, "Comparison of
Hardware Performance of Selected Phase 2 eSTREAM Candidates,"
Proc. SASC 2007: Stream Ciphers Revisited, ECRYPT eSTREAM
workshop, Bochum, Germany, Jan. 31-Feb. 1, 2007. (paper +
slides)

- C. Shu, S. Kwon, K. Gaj, "FPGA Accelerated Tate Pairing Based
Cryptosystems over Binary Fields," Proc. IEEE 2005 Conference on
Field Programmable Technology, FPT'06, Bangkok, Dec. 13-15,
2006. (paper + slides)

- K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M.
Khaleeluddin, R. Bachimanchi, "Implementing the Elliptic Curve
Method of Factoring in Reconfigurable Hardware," CHES 2006,
Cryptographic Hardware and Embedded Systems workshop, Yokohama,
Japan, Oct 10-13, 2006. (paper +
slides)

- K. Gaj, S. Kwon, P. Baier, P. Kohlbrenner, H. Le, M.
Khaleeluddin, R. Bachimanchi, "Implementing the Elliptic Curve
Method of Factoring in Reconfigurable Hardware," Proc. Special
Purpose Hardware for Attacking Cryptographic Systems, SHARCS
2006, Cologne, Germany, Apr. 3-4, 2006. (paper
+ slides)

- D. Misra and K. Gaj, "Face Recognition CAPTCHAs," Proc.
Advanced International Conference on Telecommunications and
International Conference on Internet and Web Applications and
Services, AICT/ICIW 2006, 19-25 February 2006, Guadeloupe,
French Caribbean (paper).

- E. El-Araby, M. Taher, K. Gaj, T. El-Ghazawi, D. Caliga, N.
Alexandridis, "System-Level Parallelism and Concurrency
Maximization in Reconfigurable Computing Applications,"
*International Journal of Embedded Systems*(IJES), vol. 2, no.1/2, pp. 62-72, 2006. (paper)

- A. S. Zeineddini and K. Gaj, "Secure Partial Reconfiguration
of FPGAs," Proc. IEEE 2005 Conference on Field Programmable
Technology, FPT'05, Singapore, Dec. 11-14, 2005. (paper + slides)

- C. Zouridaki, M. Hejmo, B. L. Mark, R. K. Thomas, K. Gaj,
"Analysis of Attacks and Defense Mechanisms for QoS Signaling,"
Proc. 4th International Workshop on Wireless Information
Systems, WIS 2005, in conjunction with ICEIS 2005, Miami, USA,
May 2005, pp. 61-70. (paper + slides)

- S. Bajracharya, D. Misra, K. Gaj, T. El-Ghazawi ,
"Reconfigurable Hardware Implementation of Mesh Routing in
Number Field Sieve Factorization," Proc. Special Purpose
Hardware for Attacking Cryptographic Systems, SHARCS 2005,
Paris, France, Feb. 24-25, 2005, pp. 71-81. (paper
+ slides)

- H. Kurnio, H. Wang, J. Pieprzyk, K. Gaj, "Securing Multicast
Groups in Ad Hoc Networks," in LNCS 3309, Advanced Workshop on
Content Computing, AWCC 2004, ZhenJiang, JiangSu, China,
November 15-17, 2004, pp. 194-207. (paper)

- S. Bajracharya, D. Misra, K. Gaj, T. El-Ghazawi,
"Reconfigurable Hardware Implementation of Mesh Routing in
Number Field Sieve Factorization," Proc. IEEE 2004 Conference on
Field Programmable Technology, FPT 2004, Brisbane, Australia,
Dec. 6-8, 2004, pp. 263-270. (paper + slides)

- T. El-Ghazawi, K. Gaj, N. Alexandridis, F. Vroman, N. Nguyen,
J. R. Radzikowski, P. Samipagdi, and S. A. Suboh, "An Empirical
Comparative Study of Job Management Systems," Concurrency:
Practice and Experience, vol. 16, no. 13, Nov. 2004, pp.
1229-1246. (paper)

- S. Kwon, K. Gaj, C.-H. Kim, C.-P. Hong, "Efficient Linear
Array for Multiplication in GF(2
^{m}) Using a Normal Basis for Elliptic Curve Cryptography," in LNCS 3156, Cryptographic Hardware and Embedded Systems - CHES 2004, Cambridge, MA, USA, Aug. 2004, pp. 76-91. (paper + slides)

- S. Bajracharya, C. Shu, K. Gaj, T. El-Ghazawi, "Implementation
of Elliptic Curve Cryptosystems over GF(2
^{n}) in Optimal Normal Basis on a Reconfigurable Computer," 14th International Conference on Field Programmable Logic and Applications, FPL 2004, Antwerp, Belgium, Aug 30 - Sept 1, 2004, pp. 1001-1005. (paper + slides)

- C. Zouridaki, B. L. Mark, K. Gaj, R. K. Thomas, "Distributed
CA-based PKI for Mobile Ad Hoc Networks Using Elliptic Curve
Cryptography," LNCS 3093, Public Key Infrastructure, First
European PKI Workshop: Research and Applications, EuroPKI 2004,
Samos Island, Greece, June 25-26, 2004, pp. 232-245. (paper
+ slides)

- E. El-Araby, M. Taher, K. Gaj, T. El-Ghazawi, D. Caliga, and
N. Alexandridis, "System-Level Parallelism and Throughput
Optimization in Designing Reconfigurable Computing
Applications", Proc. Reconfigurable Architecture Workshop, RAW
2004, Santa Fe, New Mexico, USA, April, 2004 (paper
+ slides)

- R. Lien, T. Grembowski, K. Gaj, "A 1 Gbit/s Partially Unrolled
Architecture of Hash Functions SHA-1 and SHA-512," LNCS 2964,
RSA Conference 2004, Cryptographers' Track, CT-RSA 2004, San
Francisco, CA, Feb. 2004, pp. 324-328. (paper + slides)

- P. Kohlbrenner and K. Gaj, "An Embedded True Random Number
Generator for Field Programmable Gate Arrays," Proc. ACM/SIGDA
Twelve International Symposium on Field Programmable Gate
Arrays, FPGA 2004, Monterey, CA, Feb. 2004, pp. 71-78. (paper +
slides)

- N. Nguyen, K. Gaj, D. Caliga, T. El-Ghazawi, "Implementation
of Elliptic Curve Cryptosystems on a Reconfigurable Computer,"
Proc. IEEE International Conference on Field-Programmable
Technology, FPT 2003, Tokyo, Japan, Dec. 2003, pp. 60-67. (paper + slides)

- P. Chodowiec and K. Gaj, "Very Compact FPGA Implementation of
the AES Algorithm," in LNCS 2779, Cryptographic Hardware and
Embedded Systems - CHES 2003, Cologne, Germany, Sep. 2003, pp.
319-333. (paper +
slides)

- A. Michalski, K. Gaj, T. El-Ghazawi, "An Implementation
Comparison of an IDEA Encryption Cryptosystem on Two
General-Purpose Reconfigurable Computers," LNCS 2778, 13th
International Conference on Field Programmable Logic and
Applications, FPL 2003, Lisbon, Portugal, Sep. 2003, pp.
204-219. (paper + slides)

- P. Bellows, J. Flidr, L. Gharai, C. Perkins, P. Chodowiec, and
K. Gaj, "IPsec-Protected Transport of HDTV over IP, LNCS 2778,
13th International Conference on Field Programmable Logic and
Applications, FPL 2003, Lisbon, Portugal, Sep. 2003, pp.
869-879. (paper)

- K. Gaj and A. Orlowski, "Facts and Myths of Enigma: Breaking
Stereotypes," LNCS 2656, Advances in Cryptology – EUROCRYPT
2003, Ed. E. Biham, International Conference on the Theory and
Applications of Cryptographic Techniques, EUROCRYPT 2003,
Warsaw, Poland, May 2003, pp. 106-122 (invited paper). (paper
+ slides)

- K. Gaj, T. El-Ghazawi, N. Alexandridis, J. R. Radzikowski, M.
Taher, and F. Vroman, "Effective Utilization and Reconfiguration
of Distributed Hardware Using Job Management Systems," Proc.
Reconfigurable Architecture Workshop, RAW 2003, Apr. 2003. (paper
+ slides)

- O. D. Fidanci, D. Poznanovic, K. Gaj, T. El-Ghazawi, and N.
Alexandridis, "Performance and Overhead in a Hybrid
Reconfigurable Computer," Proc. Reconfigurable Architecture
Workshop, RAW 2003, Apr. 2003. (paper
+ slides)

- T. Grembowski, R. Lien, K. Gaj, N. Nguyen, P. Bellows, J.
Flidr, T. Lehman, B. Schott, "Comparative Analysis of the
Hardware Implementations of Hash Functions SHA-1 and SHA-512,"
LNCS 2433, Information Security, Eds. G. I. Davida, Y. Frankel,
5th International Conference, ISC 2002, Sao Paulo, Brazil,
Sep./Oct. 2002, pp. 75-89. (paper
+ slides)

- K. Gaj, T. El-Ghazawi, N. Alexandridis, F. Vroman, N. Nguyen,
J. R. Radzikowski, P. Samipagdi, and S. A. Suboh, "Performance
Evaluation of Selected Job Management Systems," Proc. Workshop
on Performance Modeling, Evaluation, and Optimization of
Parallel and Distributed Systems, PMEO 2002, Fort Lauderdale,
Florida, Apr. 2002. (paper
+ slides)

- P. Chodowiec, K. Gaj, P. Bellows, and B. Schott, "Experimental
Testing of the Gigabit IPSec-Compliant Implementations of
Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board,"
LNCS 2200, Information Security, Eds. G. I. Davida, Y. Frankel,
4th International Conference, ISC 2001, Malaga, Spain, Oct.
2001, pp. 220-234. (paper
+ slides)

- M. Taher, K. Gaj, T. El-Ghazawi, and N. Alexandridis, "Job
Management System Extension To Support SLAAC-1V Reconfigurable
Hardware," Proc. 2001 MAPLD International Conference, Laurel,
Maryland, Sep. 2001. (paper
+ slides)

- A.V. Staicu, J. R. Radzikowski, K. Gaj, N. Alexandridis, and
T. El-Ghazawi, "Effective Use of Networked Reconfigurable
Resources," Proc. 2001 MAPLD International Conference, Laurel,
Maryland, Sep. 2001. (paper
+ slides)

- K. Gaj and P. Chodowiec, "Fast Implementation and Fair
Comparison of the Final Candidates for Advanced Encryption
Standard using Field Programmable Gate Arrays," LNCS 2020,
Progress in Cryptology - CT-RSA 2001, Ed. D. Naccache, RSA
Conference 2001 - Cryptographers' Track, San Francisco, Apr.
2001, pp. 84-99. (paper + slides)

- P. Chodowiec, P. Khuon, and K. Gaj, "Fast Implementations of
Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round
Pipelining," ACM/SIGDA Ninth International Symposium on Field
Programmable Gate Arrays, Monterey, CA, Feb. 2001, pp. 94-102. (paper +
slides)

- K. Gaj and P. Chodowiec, "Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware," Proc. 3rd Advanced Encryption Standard Conference, New York, April 2000, pp. 40-54. (paper + slides)

### Technical Reports

- K. Mohajerani, L. Beckwith, A. Abdulgadir, E. Ferrufino, J.-P. Kaps, and K. Gaj,
"SCA Evaluation and Benchmarking of Finalists in the NIST Lightweight Cryptography Standardization Process,"
Cryptology ePrint Archive: Report 2023/484, April 4, 2023, last revised May 5, 2023
(report).

- L. Beckwith, D.T. Nguyen, and K. Gaj,
"High-Performance Hardware Implementation of Lattice-Based Digital Signatures,"
Cryptology ePrint Archive: Report 2022/217, February 21, 2022.
(report).

- V.B. Dang, K. Mohajerani, and K. Gaj,
"High-Speed Hardware Architectures and FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber,"
Cryptology ePrint Archive: Report 2021/1508, November 14, 2021.
(report).

- K. Mohajerani, R. Haeussler, R. Nagpal, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj,
"FPGA Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process: Methodology, Metrics, Tools, and Results,"
Cryptology ePrint Archive: Report 2020/1207, October 2, 2020, last revised February 24, 2021
(report).

- V. Dang, F. Farahmand, M. Andrzejczak, K. Mohajerani, D.T. Nguyen, and K. Gaj,
"Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using Hardware and Software/Hardware Co-design Approaches,"
Cryptology ePrint Archive: Report 2020/795, June 25, 2020, last revised October 13, 2020
(report).

- J.-P. Kaps, W. Diehl, M. Tempelmeier, F. Farahmand, E. Homsirikamol, and K. Gaj,
"A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography,"
Cryptology ePrint Archive: Report 2019/1273, November 2, 2019
(report).

- F. Farahmand, M.U. Sharif, K. Briggs, and K. Gaj,
"A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES,"
Cryptology ePrint Archive: Report 2019/322, March 23, 2019
(report).

- W. Diehl, F. Farahmand, A. Abdulgadir, J.-P. Kaps, and K. Gaj,
"Face-off between the CAESAR Lightweight Finalists: ACORN vs. Ascon,"
Cryptology ePrint Archive: Report 2019/184, Feb 19, 2019, last revised March 4, 2019
(report).

- F. Farahmand, W. Diehl, A. Abdulgadir, J.-P. Kaps, and K. Gaj,
"Improved Lightweight Implementations of CAESAR Authenticated Ciphers,"
Cryptology ePrint Archive: Report 2018/573, May 31, 2018, last revised June 5, 2018
(report).

- W. Diehl, A. Abdulgadir, F. Farahmand, J.-P. Kaps, and K. Gaj,
"Comparison of Cost of Protection Against Differential Power Analysis of Selected Authenticated Ciphers,"
Cryptology ePrint Archive: Report 2018/341, April 11, 2018
(report).

- E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, P. Yalla, J.-P. Kaps, and K. Gaj
"CAESAR Hardware API," Cryptology ePrint Archive: Report 2016/626, June 14, 2016.
(report).

- E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj
"GMU Hardware API for Authenticated Ciphers," Cryptology ePrint Archive: Report 2015/669, first version - July 2015, last revised - December 6, 2015
(report).

- S. Paul, E. Homsirikamol, and K. Gaj, "A Novel
Permutation-based Hash Mode of Operation FP and the Hash
Function SAMOSA," Cryptology ePrint Archive: Report 2012/597,
Oct. 2012 (report).

- K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U.
Sharif, "Comprehensive Evaluation of High-Speed and Medium-Speed
Implementations of Five SHA-3 Finalists Using Xilinx and Altera
FPGAs," Cryptology ePrint Archive: Report 2012/368, first
version - June 2012, final version - October 2012 (report).

- M. Rogawski and K. Gaj, "Groestl Tweaks and Their Effect on
FPGA Results," Cryptology ePrint Archive: Report 2011/635, Nov.
2011 (report).

- E. Homsirikamol, M. Rogawski, and K. Gaj, "Comparing
Hardware Performance of Fourteen Round Two SHA-3 Candidates
Using FPGAs," Cryptology ePrint Archive: Report 2010/445, first
version - Aug. 2010 (report).

- K. Gaj and P. Chodowiec, "
Hardware performance of the AES finalists - survey and analysis of results,"
Technical Report, George Mason University, Sep. 2000. (report)

- P. Chodowiec and K. Gaj, "Implementations of the Twofish
Cipher Using FPGA Devices," Technical Report, George Mason
University, July 1999. (report)

- T. El-Ghazawi, K. Gaj, N. Alexandridis, B. Schott, A. V
Staicu, J. R. Radzikowski, N. Nguyen, S. A. Suboh, "Conceptual
Comparative Study of Job Management Systems," Technical Report,
George Mason University, Feb. 2001. (report + appendix)

- T. El-Ghazawi, K. Gaj, N. Alexandridis, B. Schott, A. V
Staicu, J. R. Radzikowski, N. Nguyen, J. Vongsaard, and S.
Chauvin, P. Samipagdi and S. A. Suboh, "Experimental Comparative
Study of Job Management Systems," Technical Report, George Mason
University, Jul. 2001. (report)

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